From: Namhyung Kim <namhyung@kernel.org>
To: kan.liang@linux.intel.com
Cc: peterz@infradead.org, mingo@kernel.org,
linux-kernel@vger.kernel.org, vincent.weaver@maine.edu,
eranian@google.com, ak@linux.intel.com, stable@vger.kernel.org
Subject: Re: [PATCH 1/2] perf/x86/intel: Fix a crash caused by zero PEBS status
Date: Wed, 17 Mar 2021 12:01:00 +0900 [thread overview]
Message-ID: <YFFw7OvwqN/KVzvp@google.com> (raw)
In-Reply-To: <1615555298-140216-1-git-send-email-kan.liang@linux.intel.com>
On Fri, Mar 12, 2021 at 05:21:37AM -0800, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> A repeatable crash can be triggered by the perf_fuzzer on some Haswell
> system.
> https://lore.kernel.org/lkml/7170d3b-c17f-1ded-52aa-cc6d9ae999f4@maine.edu/
>
> For some old CPUs (HSW and earlier), the PEBS status in a PEBS record
> may be mistakenly set to 0. To minimize the impact of the defect, the
> commit was introduced to try to avoid dropping the PEBS record for some
> cases. It adds a check in the intel_pmu_drain_pebs_nhm(), and updates
> the local pebs_status accordingly. However, it doesn't correct the PEBS
> status in the PEBS record, which may trigger the crash, especially for
> the large PEBS.
>
> It's possible that all the PEBS records in a large PEBS have the PEBS
> status 0. If so, the first get_next_pebs_record_by_bit() in the
> __intel_pmu_pebs_event() returns NULL. The at = NULL. Since it's a large
> PEBS, the 'count' parameter must > 1. The second
> get_next_pebs_record_by_bit() will crash.
>
> Besides the local pebs_status, correct the PEBS status in the PEBS
> record as well.
>
> Fixes: 01330d7288e0 ("perf/x86: Allow zero PEBS status with only single active event")
> Reported-by: Vince Weaver <vincent.weaver@maine.edu>
> Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Cc: stable@vger.kernel.org
Tested-by: Namhyung Kim <namhyung@kernel.org>
Thanks,
Namhyung
> ---
> arch/x86/events/intel/ds.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 7ebae18..bcf4fa5 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2010,7 +2010,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
> */
> if (!pebs_status && cpuc->pebs_enabled &&
> !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
> - pebs_status = cpuc->pebs_enabled;
> + pebs_status = p->status = cpuc->pebs_enabled;
>
> bit = find_first_bit((unsigned long *)&pebs_status,
> x86_pmu.max_pebs_events);
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-03-17 3:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-12 13:21 kan.liang
2021-03-12 13:21 ` [PATCH 2/2] perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT kan.liang
2021-03-17 12:38 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2021-03-17 3:01 ` Namhyung Kim [this message]
2021-03-17 12:38 ` [tip: perf/urgent] perf/x86/intel: Fix a crash caused by zero PEBS status tip-bot2 for Kan Liang
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