From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70BB6C433C1 for ; Wed, 24 Mar 2021 12:33:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DA2E61A06 for ; Wed, 24 Mar 2021 12:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233711AbhCXMdD (ORCPT ); Wed, 24 Mar 2021 08:33:03 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:44648 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230169AbhCXMcp (ORCPT ); Wed, 24 Mar 2021 08:32:45 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lP2gi-00CmAt-27; Wed, 24 Mar 2021 13:32:40 +0100 Date: Wed, 24 Mar 2021 13:32:40 +0100 From: Andrew Lunn To: praneeth@ti.com Cc: "David S . Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Geet Modi Subject: Re: [PATCH] net: phy: dp83867: perform soft reset and retain established link Message-ID: References: <20210324010006.32576-1-praneeth@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210324010006.32576-1-praneeth@ti.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 23, 2021 at 08:00:06PM -0500, praneeth@ti.com wrote: > From: Praneeth Bajjuri > > Current logic is performing hard reset and causing the programmed > registers to be wiped out. > > as per datasheet: https://www.ti.com/lit/ds/symlink/dp83867cr.pdf > 8.6.26 Control Register (CTRL) > do SW_RESTART to perform a reset not including the registers and is > acceptable to do this if a link is already present. I don't see any code here to determine if the like is present. What if the cable is not plugged in? > @@ -826,7 +826,7 @@ static int dp83867_phy_reset(struct phy_device *phydev) > { > int err; > > - err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); > + err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART); > if (err < 0) > return err; The code continues usleep_range(10, 20); /* After reset FORCE_LINK_GOOD bit is set. Although the * default value should be unset. Disable FORCE_LINK_GOOD * for the phy to work properly. */ return phy_modify(phydev, MII_DP83867_PHYCTRL, DP83867_PHYCR_FORCE_LINK_GOOD, 0); } Do you still need to clear the FORCE_LINK_GOOD bit after a restart? Andrew