From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CFE4C433B4 for ; Tue, 6 Apr 2021 15:21:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40485611C1 for ; Tue, 6 Apr 2021 15:21:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345594AbhDFPVw (ORCPT ); Tue, 6 Apr 2021 11:21:52 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:35960 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233393AbhDFPVt (ORCPT ); Tue, 6 Apr 2021 11:21:49 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lTnW7-00F8gN-Pt; Tue, 06 Apr 2021 17:21:23 +0200 Date: Tue, 6 Apr 2021 17:21:23 +0200 From: Andrew Lunn To: DENG Qingfang Cc: "David S. Miller" , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org, Weijie Gao , Chuanhong Guo , =?iso-8859-1?Q?Ren=E9?= van Dorst Subject: Re: [RFC net-next 1/4] net: phy: add MediaTek PHY driver Message-ID: References: <20210406141819.1025864-1-dqfext@gmail.com> <20210406141819.1025864-2-dqfext@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210406141819.1025864-2-dqfext@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 06, 2021 at 10:18:16PM +0800, DENG Qingfang wrote: > Add support for MediaTek PHYs found in MT7530 and MT7531 switches. Do you know if this PHY is available standalone? > +static int mt7531_phy_config_init(struct phy_device *phydev) > +{ > + mtk_phy_config_init(phydev); > + > + /* PHY link down power saving enable */ > + phy_set_bits(phydev, 0x17, BIT(4)); > + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); > + > + /* Set TX Pair delay selection */ > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); This gets me worried about RGMII delays. We have had bad backwards compatibility problems with PHY drivers which get RGMII delays wrong. Since this is an internal PHY, i suggest you add a test to the beginning of mt7531_phy_config_init(): if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) return -EINVAL; We can then solve RGMII problems when somebody actually needs RGMII. Andrew