From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10677C433B4 for ; Fri, 14 May 2021 14:52:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E03FD6148E for ; Fri, 14 May 2021 14:52:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234528AbhENOxr (ORCPT ); Fri, 14 May 2021 10:53:47 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:40444 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232925AbhENOxo (ORCPT ); Fri, 14 May 2021 10:53:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=AmV+EvcDeYdDnQmn67vbG6wCy+Lo347GLmfcoYF4nYU=; b=pgAhzW7y6e8e6S6CTD+RLxhtpw CIbMBW9p+nLCtjEejKjaI78U+3rS4xdSD+r6syqVKDDi5oul/aTaiVlDDHAk21Q+qcBBtRzBbitBD P33FQlRqgtMUki3Iqy1ps306xLiCE8BIMZsDHKA1FrrSh/78ephvIVnMkktqYUNAGEQk=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1lhZAw-004CPx-UN; Fri, 14 May 2021 16:52:26 +0200 Date: Fri, 14 May 2021 16:52:26 +0200 From: Andrew Lunn To: Peter Geis Cc: Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Linux Kernel Mailing List , Linux Kernel Network Developers , "open list:ARM/Rockchip SoC..." Subject: Re: [PATCH v3] net: phy: add driver for Motorcomm yt8511 phy Message-ID: References: <20210514115826.3025223-1-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > I also wonder about bits 15:12 of PHY EXT ODH: Delay and driver > > strength CFG register. > > The default value *works*, and from an emi perspective we want the > lowest strength single that is reliable. I was not meaning signal strength, but Txc_delay_sel_fe, selecte tx_clk_rgmii delay in chip which is used to latch txd_rgmii in 100BT/10BTe mode. 150ps step. Default value 15 means about 2ns clock delay compared to txd_rgmii in typical cornor. [Typos courtesy of the datasheet, not me!] This sounds like more RGMII delays. It seems like PHY EXT 0CH is about 1G mode, and PHY EXT 0DH is about 10/100 mode. I think you probably need to set this bits as well. Have you tested against a link peer at 10 Half? 100 Full? Andrew