From: Peter Zijlstra <peterz@infradead.org>
To: Like Xu <like.xu@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
linux-kernel@vger.kernel.org,
Kan Liang <kan.liang@linux.intel.com>,
Borislav Petkov <bp@alien8.de>,
seanjc@google.com, x86@kernel.org
Subject: Re: [PATCH v2 1/2] perf/x86: Skip checking if 0x0 MSR exists for guest Arch LBR
Date: Tue, 18 May 2021 11:30:54 +0200 [thread overview]
Message-ID: <YKOJTtmjvxbBJOcS@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20210430052247.3079672-1-like.xu@linux.intel.com>
On Fri, Apr 30, 2021 at 01:22:46PM +0800, Like Xu wrote:
> - Avoid checking unrelated Architecture MSR 0x0 in a simple way
I'm thinking the below is simpler still, no?
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 5272f349dca2..456aa6ffd9a1 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6250,7 +6250,8 @@ __init int intel_pmu_init(void)
> * Check all LBT MSR here.
> * Disable LBR access if any LBR MSRs can not be accessed.
> */
> - if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
> + if (x86_pmu.lbr_nr && !static_cpu_has(X86_FEATURE_ARCH_LBR) &&
> + !check_msr(x86_pmu.lbr_tos, 0x3UL))
> x86_pmu.lbr_nr = 0;
> for (i = 0; i < x86_pmu.lbr_nr; i++) {
> if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2521d03de5e0..e28892270c58 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6253,7 +6253,7 @@ __init int intel_pmu_init(void)
* Check all LBT MSR here.
* Disable LBR access if any LBR MSRs can not be accessed.
*/
- if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
+ if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
x86_pmu.lbr_nr = 0;
for (i = 0; i < x86_pmu.lbr_nr; i++) {
if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
next prev parent reply other threads:[~2021-05-18 9:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 5:22 Like Xu
2021-04-30 5:22 ` [PATCH v2 2/2] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region Like Xu
2021-05-10 2:10 ` Like Xu
2021-05-18 8:48 ` Like Xu
2021-05-18 10:02 ` Peter Zijlstra
2021-05-18 12:34 ` Like Xu
2021-05-18 13:29 ` Peter Zijlstra
2021-05-19 8:02 ` [tip: perf/urgent] perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context tip-bot2 for Like Xu
2021-05-18 9:30 ` Peter Zijlstra [this message]
2021-05-19 8:02 ` [tip: perf/urgent] perf/x86: Avoid touching LBR_TOS MSR for Arch LBR tip-bot2 for Like Xu
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