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[217.229.29.112]) by smtp.gmail.com with ESMTPSA id r21sm2991543edy.78.2021.06.04.02.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 02:31:12 -0700 (PDT) Date: Fri, 4 Jun 2021 11:32:50 +0200 From: Thierry Reding To: Dmitry Osipenko Cc: Krzysztof Kozlowski , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PULL] memory: tegra: Changes for v5.14-rc1 Message-ID: References: <20210603143739.787957-1-thierry.reding@gmail.com> <772bf62a-fb09-cec4-ed4d-ddbfc2832e2b@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="iOQBahxQkN69PIlR" Content-Disposition: inline In-Reply-To: <772bf62a-fb09-cec4-ed4d-ddbfc2832e2b@gmail.com> User-Agent: Mutt/2.0.6 (98f8cb83) (2021-03-06) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --iOQBahxQkN69PIlR Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jun 03, 2021 at 10:56:29PM +0300, Dmitry Osipenko wrote: > 03.06.2021 17:37, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > memory: tegra: Changes for v5.14-rc1 > >=20 > > This stable tag contains Dmitry's power domain work, including all the > > necessary dependencies from the regulator, clock and ARM SoC trees. > >=20 > > ---------------------------------------------------------------- > > Dmitry Osipenko (18): > > clk: tegra30: Use 300MHz for video decoder by default > > clk: tegra: Fix refcounting of gate clocks > > clk: tegra: Ensure that PLLU configuration is applied properly > > clk: tegra: Halve SCLK rate on Tegra20 > > clk: tegra: Don't allow zero clock rate for PLLs > > clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling > > clk: tegra: Mark external clocks as not having reset control > > clk: tegra: Don't deassert reset on enabling clocks > > regulator: core: Add regulator_sync_voltage_rdev() >=20 > > soc/tegra: regulators: Bump voltages on system reboot >=20 > This patch is a build dependency prerequisite for the "soc/tegra: > regulators: Support core domain state syncing" patch. Will you send a > new PR to Krzysztof with the remaining soc/tegra patches? soc/tegra patches usually go in through ARM SoC. This is merely included here because it was part of the set of patches that were needed to enable compile testing for the memory controller drivers. I've applied the remaining soc/tegra patches (12-14 of the series) to my for-5.14/soc branch but ended up not pulling that part in because it was unnecessary for the memory controller patches. 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