From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E9AC4338F for ; Sat, 14 Aug 2021 18:05:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5BA4560F92 for ; Sat, 14 Aug 2021 18:05:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238909AbhHNSFj (ORCPT ); Sat, 14 Aug 2021 14:05:39 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:50176 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238785AbhHNSFd (ORCPT ); Sat, 14 Aug 2021 14:05:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=VE21kR+EuEDNxIJsfgnVJoyX8+amKCpRdo0kK4BLWmQ=; b=E/n34eVaiz/c6PN4sSDKcRZ+WF k6G7fP0wWvVetyteNcjd4RTCACETw6XRYHHMsIi9e4hMg2RSxxyj1OlD4B6Hhxojt6wHqel+W2yHJ y2pvzxTYESLHzuUzo5wRB3OiMX2w3P84f4cKzinStHiRteFJYzQ0KboJnrdb5HdsI6/E=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mEy1f-0005it-Qr; Sat, 14 Aug 2021 20:04:55 +0200 Date: Sat, 14 Aug 2021 20:04:55 +0200 From: Andrew Lunn To: "Russell King (Oracle)" Cc: Song Yoong Siang , Marek =?iso-8859-1?Q?Beh=FAn?= , Heiner Kallweit , "David S . Miller" , Jakub Kicinski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support to WOL event Message-ID: References: <20210813084536.182381-1-yoong.siang.song@intel.com> <20210814172656.GA22278@shell.armlinux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210814172656.GA22278@shell.armlinux.org.uk> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > How does this work if the driver has no interrupt support? What is > the hardware setup this has been tested with? Hi Russell We already know from previous patches that the Intel hardware is broken, and does not actually deliver the interrupt which caused the wake up. So i assume this just continues on with the same broken hardware, but they have a different PHY connected. > What if we later want to add interrupt support to this driver to > support detecting changes in link state - isn't using this bit > in the interrupt enable register going to confict with that? Agreed. If the interrupt register is being used, i think we need this patchset to add proper interrupt support. Can you recommend a board they can buy off the shelf with the interrupt wired up? Or maybe Intel can find a hardware engineer to add a patch wire to link the interrupt output to a SoC pin that can do interrupts. Andrew