From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4653FC433EF for ; Thu, 9 Sep 2021 07:28:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C10661139 for ; Thu, 9 Sep 2021 07:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352651AbhIIH3d (ORCPT ); Thu, 9 Sep 2021 03:29:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350906AbhIIH3b (ORCPT ); Thu, 9 Sep 2021 03:29:31 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 762FBC061575; Thu, 9 Sep 2021 00:28:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=6l+bVRkZAR24KpvUarH2ZXKDkGOGMuRedBuOO37bodQ=; b=cyvi8oh3sb3R7ofchE9i+XMLVo efFEzwsvzCAxstqvZGzEkbH9IIF1L7SgHkRqw4vDdImw2c/0q+0upl0jb/oR7FhIVgZiRkwOHcpHc PGmocsa8SzH9WTdgs7sHLzjK13Hn8/VqVNGhHZzIgEWmoLJmojyuE9Xp8S1aTstN+Mtqomf9T1tJg o8ThcJdGWoLvXpb3xtLtI9cjN9AWLLWfc2Z7yo8fYBrRF1zbWttQdb48On5GFQI6SaHv8C04+Kv95 d+533NK6TyzHCLVlIbT1nsJhhsIXjixvSVxK2SdyzmmPHt8iKJi+r/Pp1SpSpqUr/yYPJzD8eG/Z5 oJq2ikLw==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1mOERB-009a4c-CB; Thu, 09 Sep 2021 07:25:49 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 049853001C0; Thu, 9 Sep 2021 09:25:30 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id DA90B2015E4B3; Thu, 9 Sep 2021 09:25:30 +0200 (CEST) Date: Thu, 9 Sep 2021 09:25:30 +0200 From: Peter Zijlstra To: Linus Torvalds Cc: Alan Stern , Alexander Shishkin , Peter Anvin , Andrea Parri , Ingo Molnar , "Paul E. McKenney" , Vince Weaver , Thomas Gleixner , Jiri Olsa , Arnaldo Carvalho de Melo , Linux Kernel Mailing List , Stephane Eranian , Will Deacon , linux-tip-commits@vger.kernel.org Subject: Re: [tip:locking/core] tools/memory-model: Add extra ordering for locks and remove it for ordinary release/acquire Message-ID: References: <20180926182920.27644-2-paulmck@linux.ibm.com> <20210908144217.GA603644@rowland.harvard.edu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 08, 2021 at 09:08:33AM -0700, Linus Torvalds wrote: > So if this is purely a RISC-V thing, Just to clarify, I think the current RISC-V thing is stonger than PowerPC, but maybe not as strong as say ARM64, but RISC-V memory ordering is still somewhat hazy to me. Specifically, the sequence: /* critical section s */ WRITE_ONCE(x, 1); FENCE RW, W WRITE_ONCE(s.lock, 0); /* store S */ AMOSWAP %0, 1, r.lock /* store R */ FENCE R, RW WRITE_ONCE(y, 1); /* critical section r */ fully separates section s from section r, as in RW->RW ordering (possibly not as strong as smp_mb() though), while on PowerPC it would only impose TSO ordering between sections. The AMOSWAP is a RmW and as such matches the W from the RW->W fence, similarly it marches the R from the R->RW fence, yielding an: RW-> W RmW R ->RW ordering. It's the stores S and R that can be re-ordered, but not the sections themselves (same on PowerPC and many others). Clarification from a RISC-V enabled person would be appreciated. > then I think it's entirely reasonable to > > spin_unlock(&r); > spin_lock(&s); > > cannot be reordered. I'm obviously completely in favour of that :-)