From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5AE0C433FE for ; Wed, 22 Sep 2021 23:40:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 989CD611C4 for ; Wed, 22 Sep 2021 23:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238463AbhIVXlm (ORCPT ); Wed, 22 Sep 2021 19:41:42 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:33010 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230145AbhIVXll (ORCPT ); Wed, 22 Sep 2021 19:41:41 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 0FF24E52; Thu, 23 Sep 2021 01:40:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1632354009; bh=gJac9EwI/a236I+4gT7/6CxMN/VTnbwyibB6JDZnL5k=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=IH7gGoI1HkWPYu+ZzvtXd6P6WKWdHjwKBqPOasrNkpBFgZ37PWGr89J0owK0RhhGS C0n6dHTLcqySJLeppWwOTW5Q8F+FsxMA9IkfyIXRUIHgAy/KjKsQ4OndXuWY9a0VwU unPRjNs2CxMfTC1cb2AFPYZkj0D10Hwe5SNtGaLg= Date: Thu, 23 Sep 2021 02:40:07 +0300 From: Laurent Pinchart To: Geert Uytterhoeven Cc: Kieran Bingham , Linux-Renesas , Kieran Bingham , Geert Uytterhoeven , Magnus Damm , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Message-ID: References: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com> <20210901235330.1611086-4-kieran.bingham@ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Tue, Sep 21, 2021 at 05:59:24PM +0200, Geert Uytterhoeven wrote: > On Thu, Sep 2, 2021 at 1:53 AM Kieran Bingham wrote: > > From: Kieran Bingham > > > > Provide the display output using the sn65dsi86 MIPI DSI bridge. > > > > Signed-off-by: Kieran Bingham > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > > @@ -66,6 +66,15 @@ memory@700000000 { > > reg = <0x7 0x00000000 0x0 0x80000000>; > > }; > > > > + reg_1p2v: regulator-1p2v { > > + compatible = "regulator-fixed"; > > + regulator-name = "fixed-1.2V"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > reg_1p8v: regulator-1p8v { > > compatible = "regulator-fixed"; > > regulator-name = "fixed-1.8V"; > > @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { > > regulator-boot-on; > > regulator-always-on; > > }; > > + > > + mini-dp-con { > > + compatible = "dp-connector"; > > + label = "CN5"; > > + type = "mini"; > > + > > + port { > > + mini_dp_con_in: endpoint { > > + remote-endpoint = <&sn65dsi86_out>; > > + }; > > + }; > > + }; > > + > > + sn65dsi86_refclk: sn65dsi86-refclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <38400000>; > > + }; > > +}; > > + > > +&dsi0 { > > + status = "okay"; > > + > > + clocks = <&cpg CPG_MOD 415>, > > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > > + <&extal_clk>; > > + clock-names = "fck", "dsi", "extal"; > > Ah, that's where the third clock was hiding ;-) > > Is this hardwired to extal, or board-specific? > In case of the former, I think it should be moved to the .dtsi. I think this is actually incorrect. The clock name, according to the bindings, is "pll", and it's documented as a 16.66MHz PLL reference clock. It comes from the CPG, but I'm not sure which clock it actually is. -- Regards, Laurent Pinchart