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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id p21sm762115oip.28.2021.09.22.13.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 13:11:07 -0700 (PDT) Received: (nullmailer pid 1210651 invoked by uid 1000); Wed, 22 Sep 2021 20:11:06 -0000 Date: Wed, 22 Sep 2021 15:11:06 -0500 From: Rob Herring To: Kavyasree Kotagiri Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, UNGLinuxDriver@microchip.com, Eugen.Hristev@microchip.com, Manohar.Puri@microchip.com Subject: Re: [PATCH v5 2/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller Message-ID: References: <20210917135142.9689-1-kavyasree.kotagiri@microchip.com> <20210917135142.9689-3-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210917135142.9689-3-kavyasree.kotagiri@microchip.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 17, 2021 at 07:21:41PM +0530, Kavyasree Kotagiri wrote: > This adds the DT bindings documentation for lan966x SoC > generic clock controller. > > Signed-off-by: Kavyasree Kotagiri > --- > v4 -> v5: > - In v4 dt-bindings, missed adding "clock-names" in required > properties and example. So, added them. > > v3 -> v4: > - Updated "clocks" description. > - Added "clock-names". > > v2 -> v3: > - Fixed dt_binding_check errors. > > v1 -> v2: > - Updated example provided for clk controller DT node. > > .../bindings/clock/microchip,lan966x-gck.yaml | 57 +++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml > > diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml > new file mode 100644 > index 000000000000..e6b4ed3b0c88 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip LAN966X Generic Clock Controller > + > +maintainers: > + - Kavyasree Kotagiri > + > +description: | > + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk, > + ddr_clk and sys_clk. This clock controller generates and supplies > + clock to various peripherals within the SoC. > + > +properties: > + compatible: > + const: microchip,lan966x-gck > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: CPU clock source > + - description: DDR clock source > + - description: System clock source > + > + clock-names: > + items: > + - const: cpu_clk > + - const: ddr_clk > + - const: sys_clk '_clk' is redundant. Drop. With that, Reviewed-by: Rob Herring > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + clks: clock-controller@e00c00a8 { > + compatible = "microchip,lan966x-gck"; > + #clock-cells = <1>; > + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; > + clock-names = "cpu_clk", "ddr_clk", "sys_clk"; > + reg = <0xe00c00a8 0x38>; > + }; > +... > -- > 2.17.1 > >