From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42726C433EF for ; Wed, 6 Oct 2021 19:32:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BFA6610C7 for ; Wed, 6 Oct 2021 19:32:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239280AbhJFTeh (ORCPT ); Wed, 6 Oct 2021 15:34:37 -0400 Received: from mail.skyhub.de ([5.9.137.197]:40796 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbhJFTef (ORCPT ); Wed, 6 Oct 2021 15:34:35 -0400 Received: from zn.tnic (p200300ec2f0d36003dde9a53b36f1ff2.dip0.t-ipconnect.de [IPv6:2003:ec:2f0d:3600:3dde:9a53:b36f:1ff2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 3AA8C1EC0409; Wed, 6 Oct 2021 21:32:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1633548762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=Sy4WTY2NLRXQm2Nup8BPLSSFgX15mIq3h1FN9sZbFd0=; b=I1k1hpqhGNKjHStuR7EfXqYlP8rRtm3P47neiuhEosVO+7H73fbwRusx/sXBsqtDOwabC5 oES1k4Zc3BRn9zC+eO/Zhn2/0BWs/baLRrRbupoH1DMhgMVupggIUAJYoRH8o7CEZVd2tA 8PdyjhdbUkV+jCOOkM1Gt75ffgj7Wvg= Date: Wed, 6 Oct 2021 21:32:38 +0200 From: Borislav Petkov To: Alex Deucher Cc: Tom Lendacky , Paul Menzel , Thomas Gleixner , Ingo Molnar , X86 ML , Dave Hansen , Andy Lutomirski , Peter Zijlstra , LKML , amd-gfx list Subject: Re: `AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y` causes AMDGPU to fail on Ryzen: amdgpu: SME is not compatible with RAVEN Message-ID: References: <8bbacd0e-4580-3194-19d2-a0ecad7df09c@molgen.mpg.de> <96f6dbed-b027-c65e-6888-c0e8630cc006@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 06, 2021 at 02:21:40PM -0400, Alex Deucher wrote: > And just another general comment, swiotlb + bounce buffers isn't > really useful on GPUs. You may have 10-100s of MBs of memory mapped > long term into the GPU's address space for random access. E.g., you > may have buffers in system memory that the display hardware is > actively scanning out of. For GPUs you should really only enable SME > if IOMMU is enabled in remapping mode. But that is probably beyond > the discussion here. Right, but insights into how these things work (or don't work) together are always welcome. And yes, as 2cc13bb4f59f says: "... The bounce buffer code has an upper limit of 256kb for the size of DMA allocations, which is too small for certain devices and causes them to fail." -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette