From: Borislav Petkov <bp@alien8.de>
To: Joerg Roedel <joro@8bytes.org>
Cc: x86@kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
hpa@zytor.com, Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Joerg Roedel <jroedel@suse.de>, Mike Rapoport <rppt@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Brijesh Singh <brijesh.singh@amd.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/4] x86/mm: Flush global TLB when switching to trampoline page-table
Date: Wed, 27 Oct 2021 11:58:45 +0200 [thread overview]
Message-ID: <YXki1Zx4jCmikBuf@zn.tnic> (raw)
In-Reply-To: <20211001154817.29225-4-joro@8bytes.org>
On Fri, Oct 01, 2021 at 05:48:16PM +0200, Joerg Roedel wrote:
> diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c
> index 31b5856010cb..b9802b18f504 100644
> --- a/arch/x86/realmode/init.c
> +++ b/arch/x86/realmode/init.c
> @@ -17,6 +17,29 @@ u32 *trampoline_cr4_features;
> /* Hold the pgd entry used on booting additional CPUs */
> pgd_t trampoline_pgd_entry;
>
> +void load_trampoline_pgtable(void)
> +{
> +#ifdef CONFIG_X86_32
> + load_cr3(initial_page_table);
> +#else
> + /* Exiting long mode will fail if CR4.PCIDE is set. */
So this comment is not valid anymore if this is a separate function - it
is valid only when that function is called in reboot.c so I guess you
should leave that comment there.
> + if (boot_cpu_has(X86_FEATURE_PCID))
> + cr4_clear_bits(X86_CR4_PCIDE);
> +
> + write_cr3(real_mode_header->trampoline_pgd);
Is there any significance to the reordering of those calls here? The
commit message doesn't say...
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-10-27 9:59 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 15:48 [PATCH v3 0/4] x86/mm: Fix some issues with using trampoline_pgd Joerg Roedel
2021-10-01 15:48 ` [PATCH v3 1/4] x86/realmode: Add comment for Global bit usage in trampline_pgd Joerg Roedel
2021-10-01 15:48 ` [PATCH v3 2/4] x86/mm/64: Flush global TLB on boot and AP bringup Joerg Roedel
2021-10-26 9:55 ` Borislav Petkov
2021-10-26 12:58 ` Borislav Petkov
2021-12-02 12:50 ` Joerg Roedel
2021-12-02 18:19 ` Borislav Petkov
2021-12-02 21:17 ` Joerg Roedel
2021-10-01 15:48 ` [PATCH v3 3/4] x86/mm: Flush global TLB when switching to trampoline page-table Joerg Roedel
2021-10-01 16:13 ` Dave Hansen
2021-10-01 17:57 ` Jörg Rödel
2021-10-27 9:58 ` Borislav Petkov [this message]
2021-12-02 12:58 ` Joerg Roedel
2021-12-02 18:26 ` Borislav Petkov
2021-10-01 15:48 ` [PATCH v3 4/4] x86/64/mm: Map all kernel memory into trampoline_pgd Joerg Roedel
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