From: Mark Brown <broonie@kernel.org>
To: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Rob Herring <robh+dt@kernel.org>, Pratyush Yadav <p.yadav@ti.com>,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v1 2/2] spi: fsl-spi: Implement trailing clock mode
Date: Mon, 28 Feb 2022 13:20:13 +0000 [thread overview]
Message-ID: <YhzMDU5kz3QERByJ@sirena.org.uk> (raw)
In-Reply-To: <f66ae24b31f10f7c3a999a77a6cfab7b2d073c6a.1645950971.git.christophe.leroy@csgroup.eu>
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On Sun, Feb 27, 2022 at 11:00:35AM +0100, Christophe Leroy wrote:
> + if (!status && spi->mode & SPI_TRAILING) {
> + struct spi_transfer t = {
> + .len = 1,
> + .tx_buf = "",
> + .bits_per_word = 4
> + };
> +
> + status = fsl_spi_setup_transfer(spi, &t);
> + if (!status)
> + status = fsl_spi_bufs(spi, &t, 0);
> + }
> + m->status = status;
This seems to be begging for a generic implementation in the core rather
than being driver specific - drivers would for the most part need
updating to advertise less than 8 bit per word transfers but the basic
operation isn't really device specific and it pretty much fits with the
existing interfaces.
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prev parent reply other threads:[~2022-02-28 13:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-27 10:00 [PATCH v1 0/2] Add support for components requiring trailing clock after transfer Christophe Leroy
2022-02-27 10:00 ` [PATCH v1 1/2] spi: Add new mode to generate additional clock cycles Christophe Leroy
2022-02-28 13:18 ` Mark Brown
2022-02-27 10:00 ` [PATCH v1 2/2] spi: fsl-spi: Implement trailing clock mode Christophe Leroy
2022-02-28 13:20 ` Mark Brown [this message]
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