From: Mark Brown <broonie@kernel.org>
To: Sameer Pujar <spujar@nvidia.com>
Cc: lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com,
oder_chiou@realtek.com, robh@kernel.org,
thierry.reding@gmail.com, jonathanh@nvidia.com,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: Re: [RFC PATCH 2/3] ASoC: rt5659: Expose internal clock relationships
Date: Thu, 10 Mar 2022 12:14:49 +0000 [thread overview]
Message-ID: <YinruZXrpP2bu7lZ@sirena.org.uk> (raw)
In-Reply-To: <1646912477-3160-3-git-send-email-spujar@nvidia.com>
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On Thu, Mar 10, 2022 at 05:11:16PM +0530, Sameer Pujar wrote:
> This patch uses standard clock bindings to establish the codec clock
> relationships. Specific configurations can be applied by DT bindings
> from codec device node. The codec driver registers PLL and MUX clocks
> to provide this flexibility.
Doesn't this need a binding document update to document what clocks are
being provided?
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next prev parent reply other threads:[~2022-03-10 12:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-10 11:41 [RFC PATCH 0/3] Flexible codec clock configuration Sameer Pujar
2022-03-10 11:41 ` [RFC PATCH 1/3] ASoC: soc-pcm: tweak DPCM BE hw_param() call order Sameer Pujar
2022-03-10 11:41 ` [RFC PATCH 2/3] ASoC: rt5659: Expose internal clock relationships Sameer Pujar
2022-03-10 12:14 ` Mark Brown [this message]
2022-03-10 11:41 ` [RFC PATCH 3/3] ASoC: tegra: Get clock rate in consumer mode Sameer Pujar
[not found] <5c531e7c-58e4-2c55-57cb-85eff68b0927@nvidia.com>
2022-03-11 13:35 ` [RFC PATCH 2/3] ASoC: rt5659: Expose internal clock relationships Mark Brown
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