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Date:   Sat, 19 Mar 2022 01:16:19 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Michael Walle <michael@walle.cc>
Cc:     "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Russell King <linux@armlinux.org.uk>, netdev@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Horatiu Vultur <horatiu.vultur@microchip.com>
Subject: Re: [PATCH net-next v3 3/3] net: mdio: mscc-miim: add lan966x
 internal phy reset support
Message-ID: <YjUg01ysbonU7L/p@lunn.ch>
References: <20220318201324.1647416-1-michael@walle.cc>
 <20220318201324.1647416-4-michael@walle.cc>
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On Fri, Mar 18, 2022 at 09:13:24PM +0100, Michael Walle wrote:
> The LAN966x has two internal PHYs which are in reset by default. The
> driver already supported the internal PHYs of the SparX-5. Now add
> support for the LAN966x, too. Add a new compatible to distinguish them.
> 
> The LAN966x has additional control bits in this register, thus convert
> the regmap_write() to regmap_update_bits() to leave the remaining bits
> untouched. This doesn't change anything for the SparX-5 SoC, because
> there, the register consists only of reset bits.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew