From: Mark Brown <broonie@kernel.org>
To: Peter Collingbourne <pcc@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: document the boot requirements for MTE
Date: Tue, 5 Apr 2022 09:04:04 +0100 [thread overview]
Message-ID: <Ykv39KMpKXb2Mr6p@sirena.org.uk> (raw)
In-Reply-To: <20220404211858.968452-1-pcc@google.com>
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On Mon, Apr 04, 2022 at 02:18:58PM -0700, Peter Collingbourne wrote:
> + For CPUs with the Memory Tagging Extension feature:
> +
> + - If EL3 is present:
> +
> + - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
> +
> + - If the kernel is entered at EL1 and EL2 is present:
> +
> + - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
Very nitpicky but this is only required for FEAT_MTE2 and above, plain
FEAT_MTE doesn't have these traps. I don't know that this is a thing
that anyone's actually implemented and from v8.7 on it's not permitted
but the above isn't strictly true if someone did for some reason have
the most basic version.
Otherwise
Reviewed-by: Mark Brown <broonie@kernel.org>
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next prev parent reply other threads:[~2022-04-05 12:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-04 21:18 Peter Collingbourne
2022-04-05 8:04 ` Mark Brown [this message]
2022-04-22 13:42 ` Catalin Marinas
2022-04-22 20:29 ` Peter Collingbourne
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