From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D129C433F5 for ; Tue, 26 Apr 2022 11:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349410AbiDZLPY (ORCPT ); Tue, 26 Apr 2022 07:15:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345831AbiDZLPT (ORCPT ); Tue, 26 Apr 2022 07:15:19 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7807578FC1 for ; Tue, 26 Apr 2022 04:12:11 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1F98DED1 for ; Tue, 26 Apr 2022 04:12:11 -0700 (PDT) Received: from e110455-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DB82E3F5A1 for ; Tue, 26 Apr 2022 04:12:10 -0700 (PDT) Date: Tue, 26 Apr 2022 12:12:00 +0100 From: Liviu Dudau To: pengfuyuan Cc: Brian Starkey , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/arm/mali-dp: Fix spelling typo in comment Message-ID: References: <20220426095106.34437-1-pengfuyuan@kylinos.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220426095106.34437-1-pengfuyuan@kylinos.cn> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 26, 2022 at 05:51:06PM +0800, pengfuyuan wrote: > Fix spelling typo in comment. > > Signed-off-by: pengfuyuan > --- > drivers/gpu/drm/arm/malidp_regs.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h > index 514c50dcb74d..59f63cc2b304 100644 > --- a/drivers/gpu/drm/arm/malidp_regs.h > +++ b/drivers/gpu/drm/arm/malidp_regs.h > @@ -145,7 +145,7 @@ > #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff > #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ > ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) > -/* Enhance coeffents reigster offset */ > +/* Enhance coeffents register offset */ You get half the cookie! :) There are actually two spelling mistakes in this comment, the other one is *coefficients*. Do you want to send an update? Best regards, Liviu > #define MALIDP_SE_IMAGE_ENH 0x3C > /* ENH_LIMITS offset 0x0 */ > #define MALIDP_SE_ENH_LOW_LEVEL 24 > -- > 2.25.1 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯