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Tue, 03 May 2022 07:49:21 -0700 (PDT) Received: from eze-laptop ([2803:9800:98c2:8470:9f4:8e2a:88e5:ec01]) by smtp.gmail.com with ESMTPSA id o20-20020a0568080bd400b00325cda1ffafsm1707597oik.46.2022.05.03.07.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 07:49:21 -0700 (PDT) Date: Tue, 3 May 2022 11:49:15 -0300 From: Ezequiel Garcia To: Benjamin Gaignard Cc: p.zabel@pengutronix.de, mchehab@kernel.org, gregkh@linuxfoundation.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, jon@nanocrew.net, aford173@gmail.com, kernel@collabora.com Subject: Re: [PATCH v3] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values Message-ID: References: <20220503135529.683474-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220503135529.683474-1-benjamin.gaignard@collabora.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 03, 2022 at 03:55:29PM +0200, Benjamin Gaignard wrote: > Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 > register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT > flag value. > The vendor code does the case to set these values. > This fix conformance test CAINIT_G_SHARP_3. > Another silly nitpick: s/fix/fixes. > Fluster HEVC score is increase by one with this patch. > > Signed-off-by: Benjamin Gaignard > --- > drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > index 6deb31b7b993..503f4b028bc5 100644 > --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) > hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); > } > > - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { > - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > - } else { > - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); > - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); > - } > + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > > hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); > hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); > -- > 2.32.0 >