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[82.27.106.168]) by smtp.gmail.com with ESMTPSA id bg30-20020a05600c3c9e00b003942a244f39sm38873wmb.18.2022.05.19.09.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 09:37:52 -0700 (PDT) Date: Thu, 19 May 2022 17:37:28 +0100 From: Jean-Philippe Brucker To: Lu Baolu Cc: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Vinod Koul , Eric Auger , Liu Yi L , Jacob jun Pan , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 05/10] arm-smmu-v3/sva: Add SVA domain support Message-ID: References: <20220519072047.2996983-1-baolu.lu@linux.intel.com> <20220519072047.2996983-6-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220519072047.2996983-6-baolu.lu@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 19, 2022 at 03:20:42PM +0800, Lu Baolu wrote: > Add support for domain ops callbacks for an SVA domain. > > Signed-off-by: Lu Baolu Reviewed-by: Jean-Philippe Brucker (I'll try to take some time next cycle to clean up the driver following this change) > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++ > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 46 +++++++++++++++++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++ > 3 files changed, 56 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index d2ba86470c42..ec77f6a51ff9 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -758,6 +758,10 @@ struct iommu_sva *arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm); > void arm_smmu_sva_unbind(struct iommu_sva *handle); > u32 arm_smmu_sva_get_pasid(struct iommu_sva *handle); > void arm_smmu_sva_notifier_synchronize(void); > +int arm_smmu_sva_attach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id); > +void arm_smmu_sva_detach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id); > #else /* CONFIG_ARM_SMMU_V3_SVA */ > static inline bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) > { > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > index f155d406c5d5..6969974ca89e 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > @@ -549,3 +549,49 @@ void arm_smmu_sva_notifier_synchronize(void) > */ > mmu_notifier_synchronize(); > } > + > +int arm_smmu_sva_attach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id) > +{ > + int ret = 0; > + struct mm_struct *mm; > + struct iommu_sva *handle; > + > + if (domain->type != IOMMU_DOMAIN_SVA) > + return -EINVAL; > + > + mm = domain_to_mm(domain); > + if (WARN_ON(!mm)) > + return -ENODEV; > + > + mutex_lock(&sva_lock); > + handle = __arm_smmu_sva_bind(dev, mm); > + if (IS_ERR(handle)) > + ret = PTR_ERR(handle); > + mutex_unlock(&sva_lock); > + > + return ret; > +} > + > +void arm_smmu_sva_detach_dev_pasid(struct iommu_domain *domain, > + struct device *dev, ioasid_t id) > +{ > + struct arm_smmu_bond *bond = NULL, *t; > + struct mm_struct *mm = domain_to_mm(domain); > + struct arm_smmu_master *master = dev_iommu_priv_get(dev); > + > + mutex_lock(&sva_lock); > + list_for_each_entry(t, &master->bonds, list) { > + if (t->mm == mm) { > + bond = t; > + break; > + } > + } > + > + if (!WARN_ON(!bond) && refcount_dec_and_test(&bond->refs)) { > + list_del(&bond->list); > + arm_smmu_mmu_notifier_put(bond->smmu_mn); > + kfree(bond); > + } > + mutex_unlock(&sva_lock); > +} > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 6e2cd082c670..4ad3ca70cf89 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2858,6 +2858,12 @@ static struct iommu_ops arm_smmu_ops = { > .page_response = arm_smmu_page_response, > .pgsize_bitmap = -1UL, /* Restricted during device attach */ > .owner = THIS_MODULE, > +#ifdef CONFIG_ARM_SMMU_V3_SVA > + .sva_domain_ops = &(const struct iommu_domain_ops) { > + .set_dev_pasid = arm_smmu_sva_attach_dev_pasid, > + .block_dev_pasid = arm_smmu_sva_detach_dev_pasid, > + }, > +#endif > .default_domain_ops = &(const struct iommu_domain_ops) { > .attach_dev = arm_smmu_attach_dev, > .map_pages = arm_smmu_map_pages, > -- > 2.25.1 >