Re: [PATCH v1] regmap: add generic indirect regmap support

[Mark Brown <broonie@kernel.org>]

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On Tue, Jun 07, 2022 at 05:27:38PM -0700, matthew.gerlach@linux.intel.com wrote:
> On Tue, 7 Jun 2022, Mark Brown wrote:
> > On Mon, Jun 06, 2022 at 09:37:55PM -0400, Tianfei Zhang wrote:
> > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

> > > This patch adds support for regmap APIs that are intended to be used by
> > > the drivers of some devices which support generic indirect register access,
> > > for example PMCI (Platform Management Control Interface) device, HSSI
> > > (High Speed Serial Interface) device in FPGA.

> > What is "generic indirect register access"?  I'm not clear what this is
> > intended to support...

> "indirect register access" is a RTL design pattern we use in FPGAs
> frequently.  The design pattern involves a small number of registers plus a
> little handshake code to access various register spaces inside the FPGA
> fabric.  The design pattern is "generic" in the sense that the same small
> number of registers and handshake can be used with many different IP
> components in the FPGA.  Historically, the bit definitions and handshaking
> was slightly different for each IP component.  This is an attempt at a
> consistent usage across IP components.

> Would a different name help?

This wouldn't address the major problem which is...

> > > +	writel(0, ctx->base + INDIRECT_CMD_OFF);
> > > +	ret = readl_poll_timeout((ctx->base + INDIRECT_CMD_OFF), cmd,
> > > +				 (!cmd), INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
> > > +	if (ret)
> > > +		dev_err(ctx->dev, "%s timed out on clearing cmd 0x%xn", __func__, cmd);

> > ...and this doesn't look particularly generic, it looks like it's for
> > some particular controller/bridge?

...that this appears to be entirely specific to some particular device,
it's got things like hard coded register addresses and timeouts which
mean it can't be reused.

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