From: Sean Christopherson <seanjc@google.com>
To: Like Xu <like.xu.linux@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Jim Mattson <jmattson@google.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Like Xu <likexu@tencent.com>
Subject: Re: [PATCH 3/7] KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_mask
Date: Thu, 21 Jul 2022 18:27:04 +0000 [thread overview]
Message-ID: <YtmaeO85VAopC4BH@google.com> (raw)
In-Reply-To: <84e1a911-d4f9-8984-a548-62100aafd035@gmail.com>
On Thu, Jul 21, 2022, Like Xu wrote:
> On 21/7/2022 8:45 am, Sean Christopherson wrote:
> > On Wed, Jul 13, 2022, Like Xu wrote:
> > > From: Like Xu <likexu@tencent.com>
> > >
> > > In the extreme case of host counters multiplexing and contention, the
> > > perf_event requested by the guest's pebs counter is not allocated to any
> > > actual physical counter, in which case hw.idx is bookkept as -1,
> > > resulting in an out-of-bounds access to host_cross_mapped_mask.
> > >
> > > Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations")
> > > Signed-off-by: Like Xu <likexu@tencent.com>
> > > ---
> > > arch/x86/kvm/vmx/pmu_intel.c | 11 +++++------
> > > 1 file changed, 5 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> > > index 53ccba896e77..1588627974fa 100644
> > > --- a/arch/x86/kvm/vmx/pmu_intel.c
> > > +++ b/arch/x86/kvm/vmx/pmu_intel.c
> > > @@ -783,20 +783,19 @@ static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
> > > void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu)
> > > {
> > > struct kvm_pmc *pmc = NULL;
> > > - int bit;
> > > + int bit, hw_idx;
> > > for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl,
> > > X86_PMC_IDX_MAX) {
> > > pmc = intel_pmc_idx_to_pmc(pmu, bit);
> > > if (!pmc || !pmc_speculative_in_use(pmc) ||
> > > - !intel_pmc_is_enabled(pmc))
> > > + !intel_pmc_is_enabled(pmc) || !pmc->perf_event)
> > > continue;
> > > - if (pmc->perf_event && pmc->idx != pmc->perf_event->hw.idx) {
> > > - pmu->host_cross_mapped_mask |=
> > > - BIT_ULL(pmc->perf_event->hw.idx);
> > > - }
> > > + hw_idx = pmc->perf_event->hw.idx;
> > > + if (hw_idx != pmc->idx && hw_idx != -1)
> >
> > How about "hw_idx > 0" so that KVM is a little less dependent on perf's exact
> > behavior? A comment here would be nice too.
>
> The "hw->idx = 0" means that it occupies counter 0, so this part will look
> like this:
Doh, typo on my part, meant "hw_idx >= 0". "> -1" is ok, though it's definitely
less idiomatic:
$ git grep ">= 0" | wc -l
5679
$ git grep "> -1" | wc -l
66
next prev parent reply other threads:[~2022-07-21 18:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 12:24 [PATCH 0/7] KVM: x86/pmu: Fix some corner cases including Intel PEBS Like Xu
2022-07-13 12:25 ` [PATCH 1/7] perf/x86/core: Update x86_pmu.pebs_capable for ICELAKE_{X,D} Like Xu
2022-07-13 12:25 ` [PATCH 2/7] perf/x86/core: Completely disable guest PEBS via guest's global_ctrl Like Xu
2022-07-13 12:25 ` [PATCH 3/7] KVM: x86/pmu: Avoid setting BIT_ULL(-1) to pmu->host_cross_mapped_mask Like Xu
2022-07-21 0:45 ` Sean Christopherson
2022-07-21 2:02 ` Like Xu
2022-07-21 18:27 ` Sean Christopherson [this message]
2022-07-13 12:25 ` [PATCH 4/7] KVM: x86/pmu: Not to generate PEBS records for emulated instructions Like Xu
2022-07-21 0:51 ` Sean Christopherson
2022-07-21 2:22 ` Like Xu
2022-07-13 12:25 ` [PATCH 5/7] KVM: x86/pmu: Avoid using PEBS perf_events for normal counters Like Xu
2022-07-13 12:25 ` [PATCH 6/7] KVM: x86/pmu: Defer reprogram_counter() to kvm_pmu_handle_event() Like Xu
2022-07-13 12:25 ` [PATCH 7/7] KVM: x86/pmu: Defer counter emulated overflow via pmc->stale_counter Like Xu
2022-07-13 12:25 ` [kvm-unit-tests PATCH] x86: Add tests for Guest Processor Event Based Sampling (PEBS) Like Xu
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