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From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, kan.liang@intel.com,
	ak@linux.intel.com, acme@redhat.com, namhyung@kernel.org,
	irogers@google.com
Subject: Re: [PATCH] perf/x86/intel/ds: fix precise store latency handling
Date: Thu, 18 Aug 2022 10:36:30 +0200	[thread overview]
Message-ID: <Yv36DrUKLz8UWnbX@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20220818054613.1548130-1-eranian@google.com>

On Wed, Aug 17, 2022 at 10:46:13PM -0700, Stephane Eranian wrote:
> With the existing code in store_latency_data(), the memory operation (mem_op)
> returned to the user is always OP_LOAD where in fact, it should be OP_STORE.
> This comes from the fact that the function is simply grabbing the information
> from a data source map which covers only load accesses. Intel 12th gen CPU
> offers precise store sampling that captures both the data source and latency.
> Therefore it can use the data source mapping table but must override the
> memory operation to reflect stores instead of loads.
> 
> Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
> Signed-off-by: Stephane Eranian <eranian@google.com>

Thanks

  reply	other threads:[~2022-08-18  8:36 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-18  5:46 Stephane Eranian
2022-08-18  8:36 ` Peter Zijlstra [this message]
2022-08-22  9:00 ` [tip: perf/urgent] perf/x86/intel/ds: Fix " tip-bot2 for Stephane Eranian

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