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[66.111.4.227]) by smtp.gmail.com with ESMTPSA id bp19-20020a05622a1b9300b00342fdc4004fsm10370308qtb.52.2022.08.16.09.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Aug 2022 09:43:47 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailauth.nyi.internal (Postfix) with ESMTP id ABA4A27C0071; Tue, 16 Aug 2022 12:43:46 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Tue, 16 Aug 2022 12:43:46 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdehgedguddthecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhq uhhnucfhvghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrf grthhtvghrnhephedugfduffffteeutddvheeuveelvdfhleelieevtdeguefhgeeuveei udffiedvnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh epsghoqhhunhdomhgvshhmthhprghuthhhphgvrhhsohhnrghlihhthidqieelvdeghedt ieegqddujeejkeehheehvddqsghoqhhunhdrfhgvnhhgpeepghhmrghilhdrtghomhesfh higihmvgdrnhgrmhgv X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 16 Aug 2022 12:43:44 -0400 (EDT) Date: Tue, 16 Aug 2022 09:43:29 -0700 From: Boqun Feng To: Hector Martin Cc: Will Deacon , Linus Torvalds , Herbert Xu , Tejun Heo , peterz@infradead.org, jirislaby@kernel.org, maz@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, oneukum@suse.com, roman.penyaev@profitbricks.com, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH] workqueue: Fix memory ordering race in queue_work*() Message-ID: References: <20220816134156.GB11202@willie-the-truck> <74559da4-5cd4-7cc4-0303-ab5f6a8b92ae@marcan.st> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <74559da4-5cd4-7cc4-0303-ab5f6a8b92ae@marcan.st> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 17, 2022 at 01:22:09AM +0900, Hector Martin wrote: > On 16/08/2022 23.55, Boqun Feng wrote: > > On Tue, Aug 16, 2022 at 02:41:57PM +0100, Will Deacon wrote: > >> It's worth noting that with the spinlock-based implementation (i.e. > >> prior to e986a0d6cb36) then we would have the same problem on > >> architectures that implement spinlocks with acquire/release semantics; > >> accesses from outside of the critical section can drift in and reorder > >> with each other there, so the conversion looked legitimate to me in > >> isolation and I vaguely remember going through callers looking for > >> potential issues. Alas, I obviously missed this case. > >> > > > > I just to want to mention that although spinlock-based atomic bitops > > don't provide the full barrier in test_and_set_bit(), but they don't > > have the problem spotted by Hector, because test_and_set_bit() and > > clear_bit() sync with each other via locks: > > > > test_and_set_bit(): > > lock(..); > > old = *p; // mask is already set by other test_and_set_bit() > > *p = old | mask; > > unlock(...); > > clear_bit(): > > lock(..); > > *p ~= mask; > > unlock(..); > > > > so "having a full barrier before test_and_set_bit()" may not be the > > exact thing we need here, as long as a test_and_set_bit() can sync with > > a clear_bit() uncondiontally, then the world is safe. For example, we > > can make test_and_set_bit() RELEASE, and clear_bit() ACQUIRE on ARM64: > > > > test_and_set_bit(): > > atomic_long_fetch_or_release(..); // pair with clear_bit() > > // guarantee everything is > > // observed. > > clear_bit(): > > atomic_long_fetch_andnot_acquire(..); > > > > , maybe that's somewhat cheaper than a full barrier implementation. > > > > Thoughts? Just to find the exact ordering requirement for bitops. > > It's worth pointing out that the workqueue code does *not* pair > test_and_set_bit() with clear_bit(). It does an atomic_long_set() > instead (and then there are explicit barriers around it, which are > expected to pair with the implicit barrier in test_and_set_bit()). If we > define test_and_set_bit() to only sync with clear_bit() and not > necessarily be a true barrier, that breaks the usage of the workqueue code. > Ah, I miss that, but that means the old spinlock-based atomics are totally broken unless spinlock means full barriers on these archs. But still, if we define test_and_set_bit() as RELEASE atomic instead of a full barrier + atomic, it should work for workqueue, right? Do we actually need extra ordering here? WRITE_ONCE(*x, 1); // A test_and_set_bit(..); // a full barrier will order A & B WRITE_ONCE(*y, 1); // B That's something I want to figure out. Regards, Boqun > - Hector