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X-CSE-ConnectionGUID: AvwDpnVCSoC4VAB5ushNwQ== X-CSE-MsgGUID: jzOD0vykTRaXuI3soHWV6g== X-IronPort-AV: E=McAfee;i="6700,10204,11382"; a="43867246" X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="43867246" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:22:12 -0700 X-CSE-ConnectionGUID: sUVwKoHDQxyIOIn75Tj2xw== X-CSE-MsgGUID: 4tE2DzzsS9mDO64YU8DZ3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,271,1736841600"; d="scan'208";a="124916036" Received: from smile.fi.intel.com ([10.237.72.58]) by orviesa008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 00:22:08 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.98) (envelope-from ) id 1twc8K-00000005Gbk-2ZyD; Mon, 24 Mar 2025 09:22:04 +0200 Date: Mon, 24 Mar 2025 09:22:04 +0200 From: Andy Shevchenko To: mailhol.vincent@wanadoo.fr Cc: Yury Norov , Lucas De Marchi , Rasmus Villemoes , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , David Airlie , Simona Vetter , Andrew Morton , linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Andi Shyti , David Laight , Jani Nikula Subject: Re: [PATCH v7 1/5] bits: introduce fixed-type GENMASK_U*() Message-ID: References: <20250322-fixed-type-genmasks-v7-0-da380ff1c5b9@wanadoo.fr> <20250322-fixed-type-genmasks-v7-1-da380ff1c5b9@wanadoo.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250322-fixed-type-genmasks-v7-1-da380ff1c5b9@wanadoo.fr> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Sat, Mar 22, 2025 at 06:23:12PM +0900, Vincent Mailhol via B4 Relay wrote: > > Add GENMASK_TYPE() which generalizes __GENMASK() to support different > types, and implement fixed-types versions of GENMASK() based on it. > The fixed-type version allows more strict checks to the min/max values > accepted, which is useful for defining registers like implemented by > i915 and xe drivers with their REG_GENMASK*() macros. > > The strict checks rely on shift-count-overflow compiler check to fail > the build if a number outside of the range allowed is passed. > Example: > > #define FOO_MASK GENMASK_U32(33, 4) > > will generate a warning like: > > include/linux/bits.h:51:27: error: right shift count >= width of type [-Werror=shift-count-overflow] > 51 | type_max(t) >> (BITS_PER_TYPE(t) - 1 - (h))))) > | ^~ > > While GENMASK_TYPE() is crafted to cover all variants, including the > already existing GENMASK(), GENMASK_ULL() and GENMASK_U128(), for the > moment, only use it for the newly introduced GENMASK_U*(). The > consolidation will be done in a separate change. ... > #if !defined(__ASSEMBLY__) > + > -#else > +#else /* defined(__ASSEMBLY__) */ > -#endif > + > +#endif /* !defined(__ASSEMBLY__) */ Up to you, but if new version is needed or maintainer require, I would move the above changes either to a separate patch (prerequisite) or dropped them at all. These are not big but unneeded churn, -- With Best Regards, Andy Shevchenko