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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47782a10459sm68534151cf.4.2025.04.01.11.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Apr 2025 11:03:49 -0700 (PDT) Date: Tue, 1 Apr 2025 14:03:47 -0400 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, "Fabio M. De Francesco" , Terry Bowman Subject: Re: [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region Message-ID: References: <20250218132356.1809075-1-rrichter@amd.com> <20250218132356.1809075-11-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250218132356.1809075-11-rrichter@amd.com> On Tue, Feb 18, 2025 at 02:23:51PM +0100, Robert Richter wrote: > Endpoints requiring address translation might not be aware of the > system's interleaving configuration. Instead, interleaving can be > configured on an upper memory domain (from an endpoint view) and thus > is not visible to the endpoint. For region creation this might cause > an invalid interleaving config that does not match the CFMWS entries. > > Use the interleaving configuration of the root decoders to create a > region which bases on CFMWS entries. This always matches the system's > interleaving configuration and is independent of the underlying memory > topology. > > Signed-off-by: Robert Richter ... snip ... > @@ -1955,12 +1971,23 @@ static int cxl_port_calc_interleave(struct cxl_port *port, > if (is_cxl_root(port)) > return 0; > > - rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways); > + rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways, > + &parent_granularity); > if (rc) > return rc; > > ctx->pos = ctx->pos * parent_ways + parent_pos; > > + if (ctx->interleave_ways) > + ctx->interleave_ways *= parent_ways; > + else > + ctx->interleave_ways = parent_ways; > + > + if (ctx->interleave_granularity) > + ctx->interleave_granularity *= ctx->interleave_ways; > + else > + ctx->interleave_granularity = parent_granularity; > + > return ctx->pos; > } The root is always build from the CFMWS, so you don't need to do any math, you just need to take the root. Since the logic calling this will always climb to the root, you'll always get the right value. So I think you just want this --- diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index fe23dc106956..05b24b008a1b 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1977,17 +1977,8 @@ static int cxl_port_calc_interleave(struct cxl_port *port, return rc; ctx->pos = ctx->pos * parent_ways + parent_pos; - - if (ctx->interleave_ways) - ctx->interleave_ways *= parent_ways; - else - ctx->interleave_ways = parent_ways; - - if (ctx->interleave_granularity) - ctx->interleave_granularity *= ctx->interleave_ways; - else - ctx->interleave_granularity = parent_granularity; - + ctx->interleave_ways = parent_ways; + ctx->interleave_granularity = parent_granularity; return ctx->pos; }