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Mon, 16 Dec 2024 06:19:55 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BG6JsEh028720 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 16 Dec 2024 06:19:54 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 15 Dec 2024 22:19:50 -0800 Date: Mon, 16 Dec 2024 14:19:46 +0800 From: Yuanjie Yang To: Konrad Dybcio , , , , , , , CC: , , , , , Subject: Re: [PATCH v4 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Message-ID: References: <20241206023711.2541716-1-quic_yuanjiey@quicinc.com> <20241206023711.2541716-2-quic_yuanjiey@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wK_5kkYM0373_DNMUynYso8GRqRt3TFd X-Proofpoint-ORIG-GUID: wK_5kkYM0373_DNMUynYso8GRqRt3TFd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412160049 On Fri, Dec 13, 2024 at 01:56:04PM +0100, Konrad Dybcio wrote: > On 6.12.2024 3:37 AM, Yuanjie Yang wrote: > > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. > > > > Signed-off-by: Yuanjie Yang > > --- > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 209 +++++++++++++++++++++++++++ > > 1 file changed, 209 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > index 590beb37f441..e52bf8c77884 100644 > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > @@ -399,6 +399,72 @@ qfprom: efuse@780000 { > > #size-cells = <1>; > > }; > > > > + sdhc_1: mmc@7c4000 { > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0x0 0x007c4000 0x0 0x1000>, > > + <0x0 0x007c5000 0x0 0x1000>, > > + <0x0 0x007c8000 0x0 0x8000>; > > + reg-names = "hc", > > + "cqhci", > > + "ice"; > > + > > + interrupts = , > > + ; > > + interrupt-names = "hc_irq", > > + "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > + <&gcc GCC_SDCC1_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>, > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > + clock-names = "iface", > > + "core", > > + "xo", > > + "ice"; > > + > > + resets = <&gcc GCC_SDCC1_BCR>; > > + > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc1_opp_table>; > > + iommus = <&apps_smmu 0x02c0 0x0>; > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > QCOM_ICC_TAG_ACTIVE_ONLY for the CPU path OK, I will fix it in next patch. > > + interconnect-names = "sdhc-ddr", > > + "cpu-sdhc"; > > + > > + qcom,dll-config = <0x000f642c>; > > + qcom,ddr-config = <0x80040868>; > > + supports-cqe; > > + dma-coherent; > > + status = "disabled"; > > Nit: please add a newline before status for consistency I will add a newline before status in next patch. > (both comments apply to both controllers) OK I will fix both controllers(SDHC_1 and SDHC_2). > Konrad Thanks, yuanjie