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charset=us-ascii Content-Disposition: inline In-Reply-To: On 24-12-12 18:34:37, Konrad Dybcio wrote: > On 12.12.2024 5:50 PM, Abel Vesa wrote: > > The X Elite platform features two SDHC v5 controllers. > > > > Describe the controllers along with the pin configuration in TLMM > > for the SDC2, since they are hardwired and cannot be muxed to any > > other function. The SDC4 pin configuration can be muxed to different > > functions, so leave those to board specific dts. > > > > Signed-off-by: Abel Vesa > > --- > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 142 +++++++++++++++++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..1584df66ea915230995f0cf662cde813f4ae02a1 100644 > > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > > @@ -4094,6 +4094,108 @@ lpass_lpicx_noc: interconnect@7430000 { > > #interconnect-cells = <2>; > > }; > > > > + sdhc_2: mmc@8804000 { > > + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0 0x08804000 0 0x1000>; > > + > > + interrupts = , > > + ; > > + interrupt-names = "hc_irq", "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > > + <&gcc GCC_SDCC2_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", "core", "xo"; > > + iommus = <&apps_smmu 0x520 0>; > > + qcom,dll-config = <0x0007642c>; > > + qcom,ddr-config = <0x80040868>; > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc2_opp_table>; > > + > > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; > > The comment regarding ICC defines from v3 still stands Urgh, missed that one. Will respin next week with that addressed as well. > > the rest of the patch looks good > > Konrad Thanks for reviewing! Abel