From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63BF717B50A for ; Tue, 7 Jan 2025 16:41:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736268098; cv=none; b=I8AMJm7nnHAJIL77OOyh/WYp77eJ/drmp3MiGVUgbXp8CqwSsvMXlkZCf2BU8j7O5OSa5vAjwgiCCsZuAS1xHKhDfVXB2PvMA9Po3GojgD/Kivvq88M89pEF5VIZq3BtTm2J4mFQqDjIM9GcN9pmE7qJ/fGzPyHCCCSNk/YQJO0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736268098; c=relaxed/simple; bh=DhxodWASVm/kI/9qqqAewVyTnAtec2XTB5Ogt4UIWo4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=T5+rhCLmW3JLnokFXoRODUOkiTHJRfUXciMsmyKBHfcLguPiQpDy0/Mq7wcSj1Qa7ReoDulfm3Qo5rh/+iMfnVGymHeFi1cLa7eJs8U82k3AIoMEmQpv+8o6Iy3b+x7T3tWZ4dnLdS+wwEiaWLnGdaQ/Nqg4vv4NMC2C8/VPmJs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1tVCe3-0001fn-L2; Tue, 07 Jan 2025 17:41:31 +0100 Received: from pty.whiteo.stw.pengutronix.de ([2a0a:edc0:2:b01:1d::c5]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tVCe1-007NN0-2p; Tue, 07 Jan 2025 17:41:30 +0100 Received: from ore by pty.whiteo.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1tVCe2-009cbp-1h; Tue, 07 Jan 2025 17:41:30 +0100 Date: Tue, 7 Jan 2025 17:41:30 +0100 From: Oleksij Rempel To: Andrew Lunn Cc: Maxime Chevallier , "Russell King (Oracle)" , Kory Maincent , davem@davemloft.net, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com, Jakub Kicinski , Eric Dumazet , Paolo Abeni , linux-arm-kernel@lists.infradead.org, Christophe Leroy , Herve Codina , Florian Fainelli , Heiner Kallweit , Vladimir Oltean , Marek =?utf-8?B?QmVow7pu?= , =?utf-8?Q?Nicol=C3=B2?= Veronese , Simon Horman , mwojtas@chromium.org, Antoine Tenart Subject: Re: [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Message-ID: References: <20241220201506.2791940-1-maxime.chevallier@bootlin.com> <20250107142605.6c605eaf@kmaincent-XPS-13-7390> <20250107171507.06908d71@fedora.home> <601067b3-2f8a-4080-9141-84a069db276e@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <601067b3-2f8a-4080-9141-84a069db276e@lunn.ch> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org On Tue, Jan 07, 2025 at 05:22:51PM +0100, Andrew Lunn wrote: > > I have however seen devices that have a 1G PHY connected to a RJ45 > > port with 2 lanes only, thus limiting the max achievable speed to 100M. > > Here, we would explicietly describe the port has having 2 lanes. I can confirm existence of this kind of designs. One industrial real life example: a SoC connected to 3 port Gigabit KSZ switch. One port is typical RJ45 connector. Other port is RJ11 connector. The speed can be reduced by using max-speed property. But i can't provide any user usable diagnostic information just by saying pair A or B is broken. This is one of the reasons why i propose detailed description. > Some PHYs would handle this via downshift, detecting that some pairs > are broken, and then dropping down to 100M on their own. So it is not > always necessary to have a board property, at least not for data. Ack, but it will work not for all setups. > I've no idea how this affects power transfer. Can the link partners > detect which pairs are actually wired? Not is usual simple implementation. The PSE PI devicetree properties provide enough information for a _standard_ use case. -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |