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From: Gregory Price <gourry@gourry.net>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Terry Bowman <terry.bowman@amd.com>,
	linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
Subject: Re: [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT
Date: Wed, 15 Jan 2025 12:05:29 -0500	[thread overview]
Message-ID: <Z4fq2UOUZV9yRtre@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <Z4fOrBYzIaIGCq5l@rric.localdomain>

On Wed, Jan 15, 2025 at 04:05:16PM +0100, Robert Richter wrote:
> > 
> > Should be dpa as argument? Confusing to convert an hpa to an hpa.
> 
> We need to handle the decoder address ranges, the argument is always
> the HPA range the decoder belongs to.

I see, and this is where my confusion stems from. Basically these
addresses are consider "HPA" because they are programmed to decoders,
and decoder addresses are "always HPA".

i.e. 2 interleaved devices (endpoint decoders) with normalized addresses:

dev0: base(0x0) len(0x200000000)
dev1: base(0x0) len(0x200000000)

These are HPAs because decoders are programmed with HPAs.

It's just that in this (specific) case HPA=DPA, while root decoders and
host bridge decoders will always have HPA=SPA.  We're just translating
up the stack from HPA range to HPA range.

I've been dealing with virtualization for a long time and this has been
painful for me to follow - but I think I'm getting there.

> > DPA(0)
> > dev0: base(0xc050000000) spa(0xc050000000)
> > dev1: base(0xc050000000) spa(0xc050000000)
> > 
> > DPA(0x1fffffffff)
> > dev0: base(0xc050000000) spa(0xe04fffffff)
> > dev1: base(0xc050000000) spa(0xe04fffffff)
> > 
> > The bases seems correct, the SPAs looks suspect.
> 
> SPA range length must be 0x4000000000 (2x 128G). That is, upper SPA
> must be 0x10050000000 (0xc050000000 + 0x4000000000 - 1). This one is
> too short.
> 
> The decoder range lengths below look correct (0x2000000000), the
> interleaving configuration should be checked for the decoders.
> 

If i understand correctly, this configuration may be suspect

[decoder0.0]# cat start size interleave_ways interleave_granularity
0xc050000000
0x4000000000
2             <----- root decoder reports interleave ways = 2
256

[decoder1.0]# cat start size interleave_ways interleave_granularity
0xc050000000
0x4000000000
1             <----- host bridge decoder reports interleave ways = 1
256

[decoder3.0]# cat start size interleave_ways interleave_granularity 
0xc050000000
0x4000000000
1             <----- host bridge decoder reports interleave ways = 1
256

> > I do not understand this chunk here, we seem to just be chopping the HPA
> > in half to acquire the DPA.  But the value passed in is already a DPA.
> > 
> > dpa = (0x1fffffffff & ~(256 * 2 - 1)) / 2 + (0x1fffffffff & (256 - 1))
> >     =  0xfffffffff
> 
> HPA is:
> 
>  HPA = 2 * 0x2000000000 - 1 = 0x3fffffffff
>
... snip ...
> There is probably a broken interleaving config causing half the size
> of total device mem.
>

In my case, I never see 0x3fffffffff passed in.  The value 0x1fffffffff
from the endpoint decoders is always passed in.  This suggests the host
bridge interleave ways should be 2.

I can force this and figure out why its reporting 1 and get back to you.


> > dev0 (dpa -> hpa -> spa): 0x0          -> 0x0          -> 0xc050000000
> > dev1 (dpa -> hpa -> spa): 0x0          -> 0x100        -> 0xc050000100
> > dev0 (dpa -> hpa -> spa): 0x1fffffffff -> 0x3ffffffeff -> 0x1004ffffeff
> > dev1 (dpa -> hpa -> spa): 0x1fffffffff -> 0x3fffffffff -> 0x1004fffffff
> 
> Yes, would be the result without the offset applied for spa2 above.
> The check above calculates the *total* length of hpa and spa with out
> considering the interleaving position. This is corrected using the
> offset. There is no call prm_cxl_dpa_spa(dev0, 0x1fffffffff) that
> returns 0x1004fffffff, but we want to check the upper boundery of the
> SPA range.
> 

This makes sense now, there's no dpa->spa direct translation because you
may have to go through multiple layers of translation to get there - so
the best you can do is calculate the highest possible endpoint and say
"Yeah this range is in there somewhere".

Thank you for taking the time to walk me through this, I'm sorry I've
been confused on DPA/HPA/SPA for so long - it's been a bit of a
struggle.

~Gregory

  reply	other threads:[~2025-01-15 17:05 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-07 14:09 [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Robert Richter
2025-01-07 14:09 ` [PATCH v1 01/29] cxl: Remove else after return Robert Richter
2025-01-07 16:10   ` Gregory Price
2025-01-07 16:37   ` Dave Jiang
2025-01-09 12:00     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 02/29] cxl/pci: Moving code in cxl_hdm_decode_init() Robert Richter
2025-01-07 16:18   ` Gregory Price
2025-01-29 12:47     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 03/29] cxl/pci: cxl_hdm_decode_init: Move comment Robert Richter
2025-01-07 16:46   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init() Robert Richter
2025-01-07 16:51   ` Gregory Price
2025-01-13 16:47     ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 05/29] cxl/region: Move find_cxl_root() to cxl_add_to_region() Robert Richter
2025-01-07 16:49   ` Gregory Price
2025-01-13 16:52   ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 06/29] cxl/region: Factor out code to find the root decoder Robert Richter
2025-01-07 16:57   ` Gregory Price
2025-01-13 16:59   ` Jonathan Cameron
2025-01-29 13:13     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 07/29] cxl/region: Factor out code to find a root decoder's region Robert Richter
2025-01-07 16:59   ` Gregory Price
2025-01-30 16:43     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 08/29] cxl/region: Split region registration into an initialization and adding part Robert Richter
2025-01-07 18:29   ` Gregory Price
2025-01-30 16:53     ` Robert Richter
2025-01-09  1:08   ` Li Ming
2025-01-09 10:30     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 09/29] cxl/region: Use iterator to find the root port in cxl_find_root_decoder() Robert Richter
2025-01-07 17:23   ` Gregory Price
2025-01-13 18:11   ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 10/29] cxl/region: Add function to find a port's switch decoder by range Robert Richter
2025-01-07 18:38   ` Gregory Price
2025-01-30 16:58     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-30 17:02     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 11/29] cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_initialize() Robert Richter
2025-01-07 18:41   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 12/29] cxl: Modify address translation callback for generic use Robert Richter
2025-01-07 18:44   ` Gregory Price
2025-01-31 14:19     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-31 14:27     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 13/29] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-01-07 18:47   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 14/29] cxl: Introduce parent_port_of() helper Robert Richter
2025-01-07 18:50   ` Gregory Price
2025-01-13 18:20     ` Jonathan Cameron
2025-01-07 14:10 ` [PATCH v1 15/29] cxl/region: Use an endpoint's SPA range to find a region Robert Richter
2025-01-07 19:14   ` Gregory Price
2025-02-05  8:48     ` Robert Richter
2025-01-14 10:59   ` Jonathan Cameron
2025-01-31 15:46     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05  9:00     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 16/29] cxl/region: Use translated HPA ranges to calculate the endpoint position Robert Richter
2025-01-07 22:01   ` Gregory Price
2025-02-05 10:38     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05 10:43     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 17/29] cxl/region: Rename function to cxl_find_decoder_early() Robert Richter
2025-01-07 22:06   ` Gregory Price
2025-02-05 10:56     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 18/29] cxl/region: Avoid duplicate call of cxl_find_decoder_early() Robert Richter
2025-01-07 22:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 19/29] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-01-07 22:18   ` Gregory Price
2025-02-06 10:50     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-06 11:03     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 20/29] cxl/region: Use translated HPA ranges " Robert Richter
2025-01-07 22:33   ` Gregory Price
2025-02-06 11:31     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 21/29] cxl/region: Lock decoders that need address translation Robert Richter
2025-01-07 22:35   ` Gregory Price
2025-02-06 13:23     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 22/29] cxl/region: Use translated HPA ranges to create a region Robert Richter
2025-01-07 23:08   ` Gregory Price
2025-02-06 13:25     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 23/29] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-01-13 17:48   ` Alison Schofield
2025-02-14 13:06     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 24/29] cxl/region: Use endpoint's SPA range to check " Robert Richter
2025-01-13 17:38   ` Alison Schofield
2025-02-14 13:09     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-01-07 16:32   ` Robert Richter
2025-01-07 23:28   ` Gregory Price
2025-01-08 14:52     ` Robert Richter
2025-01-08 15:49       ` Gregory Price
2025-01-08 15:48   ` Gregory Price
2025-01-09 10:14     ` Robert Richter
2025-01-14 11:13       ` Jonathan Cameron
2025-01-17  7:59         ` Robert Richter
2025-01-17 11:46           ` Jonathan Cameron
2025-01-17 14:10             ` Robert Richter
2025-01-09 22:25   ` Gregory Price
2025-01-15 15:05     ` Robert Richter
2025-01-15 17:05       ` Gregory Price [this message]
2025-01-15 22:24       ` Gregory Price
2025-01-17 14:06         ` Robert Richter
2025-01-10 22:48   ` Gregory Price
2025-01-17  8:41     ` Robert Richter
2025-01-17 21:32   ` Ben Cheatham
2025-01-28  9:29     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 26/29] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-01-07 14:10 ` [PATCH v1 27/29] cxl/region: Show message on registration failure Robert Richter
2025-01-07 23:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 28/29] cxl/region: Show message on broken target list Robert Richter
2025-01-07 23:12   ` Gregory Price
2025-01-14 11:16   ` Jonathan Cameron
2025-02-06 21:23     ` Robert Richter
2025-02-07 17:51       ` Jonathan Cameron
2025-02-12  9:08         ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 29/29] cxl: Show message when a decoder was added to a port Robert Richter
2025-01-07 23:15   ` Gregory Price
2025-01-13 18:41 ` [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Alison Schofield

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