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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250124075646.oc6ni5gp6c23ozp7@thinkpad> X-Proofpoint-GUID: chmjT6Kc13W0APEDdflh1MEGh8Pr7sB9 X-Proofpoint-ORIG-GUID: chmjT6Kc13W0APEDdflh1MEGh8Pr7sB9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_03,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 clxscore=1015 spamscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270055 On Fri, Jan 24, 2025 at 01:26:46PM +0530, Manivannan Sadhasivam wrote: > On Mon, Dec 30, 2024 at 01:24:25PM +0530, Mukesh Ojha wrote: > > For some SoCs, boot firmware is using the same IPCC instance used > > by Linux and it has kept CLEAR_ON_RECV_RD set which basically means > > interrupt pending registers are cleared when RECV_ID is read and the > > register automatically updates to the next pending interrupt/client > > status based on priority. > > > > Clear the CLEAR_ON_RECV_RD if it is set from the boot firmware. > > > > Any user visible implications due to this? > User visible impact is the case of missing interrupt. We are accessing IPCC_REG_RECV_ID register both from qcom_ipcc_irq_fn() and from qcom_ipcc_pm_resume() and for some reason if qcom_ipcc_pm_resume() run just millisecond before qcom_ipcc_irq_fn after assertion of interrupt from the remote, qcom_ipcc_pm_resume reads the IPCC_REG_RECV_ID and clears it and when the same register read from the qcom_ipcc_irq_fn() it does not see the interrupt. > > Signed-off-by: Mukesh Ojha > > --- > > Change in v2: > > - Corrected email id in the Sob. > > > > drivers/mailbox/qcom-ipcc.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c > > index 14c7907c6632..0b17a38ea6bf 100644 > > --- a/drivers/mailbox/qcom-ipcc.c > > +++ b/drivers/mailbox/qcom-ipcc.c > > @@ -14,6 +14,7 @@ > > #include > > > > /* IPCC Register offsets */ > > +#define IPCC_REG_CONFIG 0x08 > > #define IPCC_REG_SEND_ID 0x0c > > #define IPCC_REG_RECV_ID 0x10 > > #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 > > @@ -21,6 +22,7 @@ > > #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c > > #define IPCC_REG_CLIENT_CLEAR 0x38 > > > > +#define IPCC_CLEAR_ON_RECV_RD BIT(0) > > #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) > > #define IPCC_CLIENT_ID_MASK GENMASK(31, 16) > > > > @@ -274,6 +276,7 @@ static int qcom_ipcc_pm_resume(struct device *dev) > > static int qcom_ipcc_probe(struct platform_device *pdev) > > { > > struct qcom_ipcc *ipcc; > > + u32 config_value; > > static int id; > > char *name; > > int ret; > > @@ -288,6 +291,19 @@ static int qcom_ipcc_probe(struct platform_device *pdev) > > if (IS_ERR(ipcc->base)) > > return PTR_ERR(ipcc->base); > > > > + /* > > + * It is possible that boot firmware is using the same IPCC instance > > + * as of the HLOS and it has kept CLEAR_ON_RECV_RD set which basically > > + * means Interrupt pending registers are cleared when RECV_ID is read. > > + * The register automatically updates to the next pending interrupt/client > > + * status based on priority. > > + */ > > + config_value = readl(ipcc->base + IPCC_REG_CONFIG); > > + if (config_value & IPCC_CLEAR_ON_RECV_RD) { > > Can't you just clear this bit always? We can do, but i wanted to be explicit here that something been done from bootloader which Linux would need to clear. I see this patch is merged in mainline. -Mukesh > > - Mani > > -- > மணிவண்ணன் சதாசிவம்