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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e4390abbf9sm2594556d6.94.2025.02.05.12.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 12:01:59 -0800 (PST) Date: Wed, 5 Feb 2025 15:01:57 -0500 From: Gregory Price To: Smita Koralahalli Cc: linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, Ard Biesheuvel , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman Subject: Re: [PATCH v6 6/6] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Message-ID: References: <20250123084421.127697-1-Smita.KoralahalliChannabasappa@amd.com> <20250123084421.127697-7-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250123084421.127697-7-Smita.KoralahalliChannabasappa@amd.com> On Thu, Jan 23, 2025 at 08:44:21AM +0000, Smita Koralahalli wrote: > The CXL drivers use kernel trace functions for logging endpoint and > Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality > is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL > Upstream Switch Ports. > > Introduce trace logging functions for both RAS correctable and > uncorrectable errors specific to CXL PCIe Ports. Use them to trace > FW-First Protocol errors. > > Co-developed-by: Terry Bowman > Signed-off-by: Terry Bowman > Signed-off-by: Smita Koralahalli Reviewed-by: Gregory Price > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 9d4b5f39b21a..766447c169c8 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -1168,6 +1168,7 @@ static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data) > pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment, > data->prot_err.agent_addr.bus, > devfn); > + int port_type; > > if (!pdev) > return; > @@ -1176,6 +1177,18 @@ static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data) > if (pdev->driver != &cxl_pci_driver) > return; > > + port_type = pci_pcie_type(pdev); > + if (port_type == PCI_EXP_TYPE_ROOT_PORT || > + port_type == PCI_EXP_TYPE_DOWNSTREAM || > + port_type == PCI_EXP_TYPE_UPSTREAM) { Almost wish this was a macro for the sake of style, but not worth it. "corr_prot_err" and "port_prot_err" kind of blend at first glance. Not worth holding anything up. > + if (data->severity == AER_CORRECTABLE) > + cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap); > + else > + cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap); > + > + return; > + } > + > if (data->severity == AER_CORRECTABLE) > cxl_cper_trace_corr_prot_err(pdev, data->ras_cap); > else > -- > 2.17.1 >