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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c041dec129sm157964185a.18.2025.02.06.23.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 23:35:05 -0800 (PST) Date: Fri, 7 Feb 2025 02:35:03 -0500 From: Gregory Price To: Terry Bowman Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com, alucerop@amd.com Subject: Re: [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers Message-ID: References: <20250107143852.3692571-1-terry.bowman@amd.com> <20250107143852.3692571-10-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250107143852.3692571-10-terry.bowman@amd.com> On Tue, Jan 07, 2025 at 08:38:45AM -0600, Terry Bowman wrote: > Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers. > > Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a > pointer to the CXL Upstream Port's mapped RAS registers. > > Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS > register mapping. This is similar to the existing > cxl_dport_init_ras_reporting() but for USP devices. > > The USP may have multiple downstream endpoints. Before mapping AER > registers check if the registers are already mapped. > > Signed-off-by: Terry Bowman Reviewed-by: Gregory Price