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From: Oliver Upton To: =?utf-8?Q?Miko=C5=82aj?= Lenczewski Cc: ryan.roberts@arm.com, yang@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, broonie@kernel.org, mark.rutland@arm.com, james.morse@arm.com, yangyicong@hisilicon.com, robin.murphy@arm.com, anshuman.khandual@arm.com, maz@kernel.org, liaochang1@huawei.com, akpm@linux-foundation.org, david@redhat.com, baohua@kernel.org, ioworker0@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 1/3] arm64: Add BBM Level 2 cpu feature Message-ID: References: <20250219143837.44277-3-miko.lenczewski@arm.com> <20250219143837.44277-5-miko.lenczewski@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250219143837.44277-5-miko.lenczewski@arm.com> X-Migadu-Flow: FLOW_OUT Hi Miko, On Wed, Feb 19, 2025 at 02:38:38PM +0000, MikoĊ‚aj Lenczewski wrote: > +config ARM64_ENABLE_BBML2 nit: consider calling this ARM64_BBML2_NOABORT or similar, since this assumes behavior that exceeds the BBML2 baseline. > + bool "Enable support for Break-Before-Make Level 2 detection and usage" > + default y > + help > + FEAT_BBM provides detection of support levels for break-before-make > + sequences. If BBM level 2 is supported, some TLB maintenance requirements > + can be relaxed to improve performance. Selecting N causes the kernel to > + fallback to BBM level 0 behaviour even if the system supports BBM level 2. > + [...] > +static bool has_bbml2_noconflict(const struct arm64_cpu_capabilities *entry, > + int scope) > +{ > + if (!IS_ENABLED(CONFIG_ARM64_ENABLE_BBML2)) > + return false; > + > + /* We want to allow usage of bbml2 in as wide a range of kernel contexts > + * as possible. This list is therefore an allow-list of known-good > + * implementations that both support bbml2 and additionally, fulfil the typo: fullfill > + * extra constraint of never generating TLB conflict aborts when using > + * the relaxed bbml2 semantics (such aborts make use of bbml2 in certain > + * kernel contexts difficult to prove safe against recursive aborts). > + */ We should be *very* specific of what qualifies a 'known-good' implementation here. Implementations shouldn't be added to this list based on the observed behavior, only if *the implementer* states their design will not generate conflict aborts for BBML2 mapping granularity changes. > + static const struct midr_range supports_bbml2_without_abort_list[] = { > + MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), > + MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), > + {} > + }; > + > + if (!is_midr_in_range_list(read_cpuid_id(), supports_bbml2_without_abort_list)) > + return false; > + > + return true; > +} > + > #ifdef CONFIG_ARM64_PAN > static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) > { > @@ -2926,6 +2951,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) > }, > + { > + .desc = "BBM Level 2 without conflict abort", > + .capability = ARM64_HAS_BBML2_NOCONFLICT, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .matches = has_bbml2_noconflict, > + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, BBM, 2) > + }, > { > .desc = "52-bit Virtual Addressing for KVM (LPA2)", > .capability = ARM64_HAS_LPA2, > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 1e65f2fb45bd..8d67bb4448c5 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -26,6 +26,7 @@ HAS_ECV > HAS_ECV_CNTPOFF > HAS_EPAN > HAS_EVT > +HAS_BBML2_NOCONFLICT Please add this cap to cpucap_is_possible() test for the config option. Thanks, Oliver