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Thu, 27 Feb 2025 10:48:15 -0800 (PST) Date: Thu, 27 Feb 2025 19:48:11 +0100 From: Stephan Gerhold To: Konrad Dybcio , Neil Armstrong Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/3] arm64: dts: qcom: sm8650: fix PMU interrupt flag Message-ID: References: <20250227-topic-sm8650-pmu-ppi-partition-v3-0-0f6feeefe50f@linaro.org> <20250227-topic-sm8650-pmu-ppi-partition-v3-1-0f6feeefe50f@linaro.org> <7535057b-b6fc-4831-ac5b-b68903083747@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <7535057b-b6fc-4831-ac5b-b68903083747@oss.qualcomm.com> On Thu, Feb 27, 2025 at 06:50:31PM +0100, Konrad Dybcio wrote: > On 27.02.2025 5:04 PM, Neil Armstrong wrote: > > The ARM PMU interrupt is sometimes defined as IRQ_TYPE_LEVEL_LOW, > > or IRQ_TYPE_LEVEL_HIGH, but downstream and recent platforms used the > > IRQ_TYPE_LEVEL_HIGH flag so align the SM8650 definition to have a > > functional PMU working. > > > > Fixes: c8a346e408cb ("arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs") > > Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") > > Signed-off-by: Neil Armstrong > > --- > > I couldn't find anything to back this up, not inside, not on Arm's > website, but downstream agrees, so.. > The GIC doesn't really have a notion of LOW vs HIGH in the programmable registers. This is generally a design time parameter, e.g. for GIC-600: Level-sensitive PPI signals are active-LOW by default, as with previous Arm GIC implementations. However, individual PPI signals can be inverted and synchronized using parameters gic600__PPI___. https://developer.arm.com/documentation/100336/0106/components-and-configuration/redistributor/redistributor-ppi-signals For Linux it shouldn't really matter, because gic_configure_irq() ignores the polarity and looks only at IRQ_TYPE_LEVEL_MASK. If you still want this to represent the actual truth, then all hints I can find only back this down (not up) I'm afraid: Arm® Cortex®‑A520 Core Technical Reference Manual Arm® Cortex®-A720 Core Technical Reference Manual Arm® Cortex®-X4 Core Technical Reference Manual 17.2 Performance monitors interrupts When the PMU generates an interrupt, the nPMUIRQ[n] output is driven LOW. https://developer.arm.com/documentation/102517/0004/Performance-Monitors-Extension-support-/Performance-monitors-interrupts https://developer.arm.com/documentation/102530/0002/Performance-Monitors-Extension-support-/Performance-monitors-interrupts https://developer.arm.com/documentation/102484/0003/Performance-Monitors-Extension-support-/Performance-monitors-interrupts So please check if this patch is really needed, otherwise I'd suggest dropping it. Thanks, Stephan