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Thu, 06 Mar 2025 07:48:27 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:57f4:0:5485:d4b2:c087:b497]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c10437dsm2433714f8f.99.2025.03.06.07.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 07:48:26 -0800 (PST) Date: Thu, 6 Mar 2025 16:48:24 +0100 From: Simona Vetter To: Maxime Ripard Cc: Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Douglas Anderson , Herve Codina , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Subject: Re: [PATCH v5 14/16] drm/bridge: tc358768: Stop disabling when failing to enable Message-ID: Mail-Followup-To: Maxime Ripard , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Douglas Anderson , Herve Codina , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20250304-bridge-connector-v5-0-aacf461d2157@kernel.org> <20250304-bridge-connector-v5-14-aacf461d2157@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250304-bridge-connector-v5-14-aacf461d2157@kernel.org> X-Operating-System: Linux phenom 6.12.11-amd64 On Tue, Mar 04, 2025 at 12:10:57PM +0100, Maxime Ripard wrote: > The tc358768 bridge driver, if enabling it fails, tries to disable it. > This is pretty uncommon in bridge drivers, and also stands in the way > for further reworks. > > Worse, since pre_enable and enable aren't expected to fail, disable and > post_disable might be called twice: once to handle the failure, and once > to actually disable the bridge. > > Since post_disable uses regulators and clocks, this would lead to enable > count imbalances. > > In order to prevent that imbalance, and to allow further reworks, let's > drop the calls to disable and post_disable, but keep the warning to let > users know about what's going on. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Maxime Ripard Yeah proper way to clear these would be like any other link failure: - Launch async worker to do a bridge reset with the fancy new helper. - Set the link-status attribute if you can't automatically fix it and let userspace sort out the mess. Maybe we need to improve the docs a bit more? -Sima > --- > drivers/gpu/drm/bridge/tc358768.c | 10 ++-------- > 1 file changed, 2 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c > index 6db18d1e8824dd7d387211d6d1e668645cf88bbe..6b65ba8aed86012bc0f464bd5ee44325dae677c6 100644 > --- a/drivers/gpu/drm/bridge/tc358768.c > +++ b/drivers/gpu/drm/bridge/tc358768.c > @@ -1075,15 +1075,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) > val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; > val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ > tc358768_write(priv, TC358768_DSI_CONFW, val); > > ret = tc358768_clear_error(priv); > - if (ret) { > + if (ret) > dev_err(dev, "Bridge pre_enable failed: %d\n", ret); > - tc358768_bridge_disable(bridge); > - tc358768_bridge_post_disable(bridge); > - } > } > > static void tc358768_bridge_enable(struct drm_bridge *bridge) > { > struct tc358768_priv *priv = bridge_to_tc358768(bridge); > @@ -1099,15 +1096,12 @@ static void tc358768_bridge_enable(struct drm_bridge *bridge) > > /* set PP_en */ > tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); > > ret = tc358768_clear_error(priv); > - if (ret) { > + if (ret) > dev_err(priv->dev, "Bridge enable failed: %d\n", ret); > - tc358768_bridge_disable(bridge); > - tc358768_bridge_post_disable(bridge); > - } > } > > #define MAX_INPUT_SEL_FORMATS 1 > > static u32 * > > -- > 2.48.1 > -- Simona Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch