Re: [PATCH v3 net-next PATCH 1/1] net: phy: air_en8811h: Add clk provider for CKO pin

[Daniel Golle <daniel@makrotopia.org>]

Hi Lucien,

nice work, this looks much better already.

As the PHY now becomes a clk provider, please also include
linux-clk@vger.kernel.org list among the receivers in Cc for future
iterations (but allow for at least 24h to pass before resending, so
others also have time to comment on this version).

On Sun, Mar 16, 2025 at 10:19:00PM +0800, Lucien.Jheng wrote:
> The EN8811H generates 25MHz or 50MHz clocks on its CKO pin, selected by GPIO3 hardware trap.
> Register 0xcf914, read via buckpbus API, shows the frequency with bit 12: 0 for 25MHz, 1 for 50MHz.
> CKO clock output is active from power-up through md32 firmware loading.

Nit: The lines of the patch description body are still too long.

> ...
> +static int en8811h_clk_provider_setup(struct device *dev, struct clk_hw *hw)
> +{
> +	struct clk_init_data init;
> +	int ret;
> +
> +	if (!IS_ENABLED(CONFIG_COMMON_CLK))
> +		return 0;
> +
> +	init.name =  devm_kasprintf(dev, GFP_KERNEL, "%s-clk",
> +				    fwnode_get_name(dev_fwnode(dev)));
> +	if (!init.name)
> +		return -ENOMEM;
> +
> +	init.ops = &en8811h_clk_ops;
> +	init.flags = CLK_GET_RATE_NOCACHE;

The rate is fixed by bootstrap pins, so there is reason for not allowing
to cache the rate (which is always going to be the same). Hence I
suggest to not set the CLK_GET_RATE_NOCACHE flag.