Re: [PATCH v7 06/10] iio: adc: Support ROHM BD79124 ADC

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Mon, Mar 17, 2025 at 09:07:30AM +0200, Matti Vaittinen wrote:
> On 14/03/2025 16:37, Andy Shevchenko wrote:
> > On Fri, Mar 14, 2025 at 11:22:37AM +0200, Matti Vaittinen wrote:

...

> > Okay, it seems I misinterpreted the values you have in regmap configuration,
> > I was under the impression that regmap is 16-bit data, but it is about address.
> > 
> > So, we need to know why the heck HW has sparse registers
> 
> We don't know. And we really don't even need to know it. We can just use
> this device knowing there are some.

Don't you have a channel to ask HW engineers about this?

> > for what is supposed
> > to be sequential. This needs a good comment.
> 
> I think it is quite usual that devices contain undocumented registers. Not
> sure having a comment that this device also has some, adds much of value? I
> suppose I can add a comment that we can't use bulk_write because registers
> aren't in subsequent addresses - but having just removed bunch of
> unnecessary comments from the code (as requested), I'm not sure adding this
> one really improves situation... When one sees separate reads/writes for
> data spread to multiple registers, he is likely to assume addresses aren't
> subsequent.

From HW design perspective it's silly to sparse hi and lo part of
the semantically same entity. So, either the (undocumented) register
is also part of the soup, or the registers have different semantics.

This what needs to be commented in my opinion.

-- 
With Best Regards,
Andy Shevchenko