From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon()
Date: Tue, 18 Mar 2025 12:07:51 +0100 [thread overview]
Message-ID: <Z9lUB2t0eZ8bz4vW@lx-t490> (raw)
In-Reply-To: <20250317173216.GGZ9hcoDICYl1fBtBG@fat_crate.local>
Hi,
On Mon, 17 Mar 2025, Borislav Petkov wrote:
>
> On Mon, Mar 17, 2025, Ahmed S. Darwish wrote:
> > The pattern to check if an x86 vendor is AMD or HYGON (or not both) is
> > pretty common. Introduce x86_vendor_amd_or_hygon() at <asm/processor.h>
>
> So if we need to check "intel too", we do
>
> x86_vendor_amd_or_hygon_or_intel?
>
> Nah, this is silly.
>
I needed this while refactoring the cacheinfo.c leaf 0x8000001d code at
patch 11/29 ("x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d
calls") as the combined check was done multiple times.
Then I found that there are 28 other cases in the x86 tree where the
AMD/Hygon CPU vendor check is also combined. So I did that macro and it
also made a number the affected sites more succinct; e.g.:
| diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
| index 43dcd8c7badc..13df4917d7d8 100644
| --- a/arch/x86/xen/enlighten.c
| +++ b/arch/x86/xen/enlighten.c
| @@ -82,11 +82,9 @@ void xen_hypercall_setfunc(void)
| if (static_call_query(xen_hypercall) != xen_hypercall_hvm)
| return;
|
| - if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
| - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))
| - static_call_update(xen_hypercall, xen_hypercall_amd);
| - else
| - static_call_update(xen_hypercall, xen_hypercall_intel);
| + static_call_update(xen_hypercall,
| + x86_vendor_amd_or_hygon(boot_cpu_data.x86_vendor) ?
| + xen_hypercall_amd : xen_hypercall_intel);
| }
|
| /*
| @@ -118,11 +116,8 @@ noinstr void *__xen_hypercall_setfunc(void)
| if (!boot_cpu_has(X86_FEATURE_CPUID))
| xen_get_vendor();
|
| - if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
| - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON))
| - func = xen_hypercall_amd;
| - else
| - func = xen_hypercall_intel;
| + func = x86_vendor_amd_or_hygon(boot_cpu_data.x86_vendor) ?
| + xen_hypercall_amd : xen_hypercall_intel;
|
| static_call_update_early(xen_hypercall, func);
Nonetheless, I've seen your other emails in the thread, and I'll drop the
patch.
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2025-03-18 11:07 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-17 16:47 [PATCH v2 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-17 17:32 ` Borislav Petkov
2025-03-17 17:48 ` Peter Zijlstra
2025-03-17 18:10 ` Andrew Cooper
2025-03-17 18:34 ` H. Peter Anvin
2025-03-17 18:11 ` Dave Hansen
2025-03-17 18:21 ` H. Peter Anvin
2025-03-17 18:34 ` Borislav Petkov
2025-03-18 11:07 ` Ahmed S. Darwish [this message]
2025-03-19 14:47 ` H. Peter Anvin
2025-03-20 10:47 ` Ahmed S. Darwish
2025-03-17 21:42 ` Ingo Molnar
2025-03-17 21:46 ` Borislav Petkov
2025-03-17 16:47 ` [PATCH v2 02/29] x86/cpuid: Refactor <asm/cpuid.h> Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 03/29] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-17 21:36 ` Ingo Molnar
2025-03-18 11:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 04/29] x86/cacheinfo: Use CPUID leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 05/29] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 06/29] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 08/29] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 09/29] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 11/29] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 12/29] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 13/29] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 14/29] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 15/29] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 16/29] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 17/29] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 18/29] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-19 14:11 ` kernel test robot
2025-03-19 16:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 19/29] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-19 16:09 ` kernel test robot
2025-03-19 16:16 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 20/29] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 21/29] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 22/29] x86/cpu: " Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 24/29] x86/cacheinfo: Separate Intel leaf 0x4 handling Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 25/29] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 26/29] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 27/29] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 28/29] x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
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