From: Christoph Hellwig <hch@infradead.org>
To: Kelvin.Cao@microchip.com
Cc: hch@infradead.org, dmaengine@vger.kernel.org, vkoul@kernel.org,
George.Ge@microchip.com, linux-kernel@vger.kernel.org,
logang@deltatee.com
Subject: Re: [PATCH v2 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver
Date: Thu, 13 Apr 2023 22:50:07 -0700 [thread overview]
Message-ID: <ZDjpjzj3xPaeeE1c@infradead.org> (raw)
In-Reply-To: <cee60331584b0408f61652376234078d4049359c.camel@microchip.com>
On Thu, Apr 13, 2023 at 10:40:41PM +0000, Kelvin.Cao@microchip.com wrote:
> > > Why is the lock needed while reading the status and waiting
> > > for it with long delays?
> There's (low) chance of access to the same ctrl register from other
> paths which might change the value of status in an unexpected way. It
> also prevents the hardware operation from being interrupted until it
> indicates it has finished by a bit set in the status register.
Well, the lock is obviously required to protecte the reads to the
register. But why do you need to hold the lock over the reads and
the delay?
next prev parent reply other threads:[~2023-04-14 5:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-03 18:06 [PATCH v2 0/1] Switchtec Switch DMA Engine Driver Kelvin Cao
2023-04-03 18:06 ` [PATCH v2 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver Kelvin Cao
2023-04-03 20:26 ` Christophe JAILLET
2023-04-03 21:13 ` Kelvin.Cao
2023-04-10 16:42 ` Christoph Hellwig
2023-04-11 15:47 ` Logan Gunthorpe
2023-04-13 19:00 ` Kelvin.Cao
2023-04-13 22:40 ` Kelvin.Cao
2023-04-14 5:50 ` Christoph Hellwig [this message]
2023-04-14 23:08 ` Kelvin.Cao
2023-04-13 23:22 ` Kelvin.Cao
2023-04-14 5:57 ` Christoph Hellwig
2023-04-03 18:06 ` [PATCH v2 0/1] Switchtec Switch DMA Engine Driver Kelvin Cao
2023-04-03 18:06 ` [PATCH v2 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver Kelvin Cao
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