From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D474C7EE23 for ; Mon, 22 May 2023 14:59:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233278AbjEVO7V (ORCPT ); Mon, 22 May 2023 10:59:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234046AbjEVO7I (ORCPT ); Mon, 22 May 2023 10:59:08 -0400 Received: from mail11.truemail.it (mail11.truemail.it [IPv6:2001:4b7e:0:8::81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75220FD; Mon, 22 May 2023 07:58:57 -0700 (PDT) Received: from francesco-nb.int.toradex.com (31-10-206-125.static.upc.ch [31.10.206.125]) by mail11.truemail.it (Postfix) with ESMTPA id 15EA921332; Mon, 22 May 2023 16:58:51 +0200 (CEST) Date: Mon, 22 May 2023 16:58:46 +0200 From: Francesco Dolcini To: Andrew Lunn , Praneeth Bajjuri , Geet Modi , "David S. Miller" Cc: Heiner Kallweit , Russell King , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Grygorii Strashko , Dan Murphy Subject: DP83867 ethernet PHY regression Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello all, commit da9ef50f545f ("net: phy: dp83867: perform soft reset and retain established link") introduces a regression on my TI AM62 based board. I have a working DTS with Linux TI 5.10 downstream kernel branch, while testing the DTS with v6.4-rc in preparation of sending it to the mailing list I noticed that ethernet is working only on a cold poweron. With da9ef50f545f reverted it always works. Here the DTS snippet for reference: &cpsw_port1 { phy-handle = <&cpsw3g_phy0>; phy-mode = "rgmii-rxid"; }; &cpsw3g_mdio { assigned-clocks = <&k3_clks 157 20>; assigned-clock-parents = <&k3_clks 157 22>; assigned-clock-rates = <25000000>; cpsw3g_phy0: ethernet-phy@0 { compatible = "ethernet-phy-id2000.a231"; reg = <0>; interrupt-parent = <&main_gpio0>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <1000>; ti,fifo-depth = ; ti,rx-internal-delay = ; }; }; Any suggestion? Francesco