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Thu, 17 Aug 2023 11:36:20 -0700 Date: Thu, 17 Aug 2023 11:36:18 -0700 From: Nicolin Chen To: , , CC: , , , , , Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Add a user-configurable tlb_invalidate_threshold Message-ID: References: <20230816204350.29150-1-nicolinc@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230816204350.29150-1-nicolinc@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C6:EE_|PH7PR12MB8124:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b347fb6-5d85-4194-0c47-08db9f50e62a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 76iWY9Ke8JapGx8GyXecPVFBozTJE5qwhcG/TNecYZfDahEGidPvAiSdRYCju4RLLNwYqAuDgwpjtM5CW9TZzsU+COQGVIAmD/m29KyTEQmtxaAlieC1JyWgJ6i4teWSNB1hfn63houjbBXbcW7TYtkXGG6fwJZ06Dlo46rKgviCYi4yeEef6xRPoZLic8WRDeRF4fNsxwFLaWhrs8Svv2jhRqyS9yz4JM8spdgxjjwn//sKjQ/IJkagERTSwQ9UHVCMmrh92wBvx5MCTdXj2nsc520eioaAVBIZmgWI1FwqgIK0VW/LGdiGZZsUjniopsQsiuT+XG+fFYG6ZWAC7b1XDDplwSbNvtbY5uQhO9LCABZBTrOZlypmnPMRlVY2J6fi3OSBhxWdiGF+rNHlNUeat+NyOaot0hf/Xl7y91m6+Au5cjSKsUtje6csqECIe1VPn4l+pKJYWYIduA/a+fiWE4ReyRL+1rVM5U2SUD94o6/OsfMtlf6ei0lKJjxqVFD3T9ihKLpEu3opcYiu+AVsf58Z5CfQnngwvGhYoMnbHVJupLw/3RYTnHoyM6BCSeVrJIS3kOH6xXkd+rpXtQJ4/7erhQcff7Yw87Sksd9UQ/D2OmBoygl/YGRuDW26Pwp7M2WV+w/I0muELWWS2xF1LelxrHhluN94Vtyl7Us0jOv7K1a06I95Alov9qygghV0homQnMkA1qWpv1RecgThUxfZVqq9GFs8Az3v/xVWMXTcv1aJWGuRNX8xZgnA X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(39860400002)(346002)(1800799009)(186009)(82310400011)(451199024)(36840700001)(40470700004)(46966006)(55016003)(40480700001)(40460700003)(47076005)(426003)(83380400001)(2906002)(336012)(36860700001)(70206006)(70586007)(26005)(54906003)(6636002)(316002)(478600001)(5660300002)(110136005)(4326008)(9686003)(41300700001)(8936002)(8676002)(86362001)(82740400003)(33716001)(356005)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 18:36:40.9366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b347fb6-5d85-4194-0c47-08db9f50e62a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8124 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 16, 2023 at 01:43:50PM -0700, Nicolin Chen wrote: > When receiving an __arm_smmu_tlb_inv_range() call with a large size, there > could be a long latency at this function call: one part is coming from a > large software overhead in the routine of building commands, and the other > part is coming from CMDQ hardware consuming the large number of commands. > This latency could be significantly large on an SMMU that does not support > range invalidation commands, i.e. no ARM_SMMU_FEAT_RANGE_INV. > > One way to optimize this is to replace a large number of VA invalidation > commands with one single per-asid invalidation command, when the requested > size reaches a threshold. This threshold can be configurable depending on > the SMMU implementaion. I'm rethinking about this size-based threshold, since what really affects the latency is the number of the invalidation commands in the request. So having an npages-based threshold might be optimal, though the idea and implementation would be similar. Thanks Nicolin