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Date:   Mon, 7 Aug 2023 17:18:53 +0200
From:   Simon Horman <horms@kernel.org>
To:     Furong Xu <0x1207@gmail.com>
Cc:     "David S. Miller" <davem@davemloft.net>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <joabreu@synopsys.com>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Joao Pinto <jpinto@synopsys.com>, netdev@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        xfr@outlook.com, rock.xu@nio.com
Subject: Re: [PATCH] net: stmmac: xgmac: RX queue routing configuration
Message-ID: <ZNELXd4I8r+YlWXP@vergenet.net>
References: <20230807065609.1096076-1-0x1207@gmail.com>
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On Mon, Aug 07, 2023 at 02:56:09PM +0800, Furong Xu wrote:
> Commit abe80fdc6ee6 ("net: stmmac: RX queue routing configuration")
> introduced RX queue routing to DWMAC4 core.
> This patch extend the support to XGMAC2 core.
> 
> Signed-off-by: Furong Xu <0x1207@gmail.com>

Hi Furong Xu,

as this is a feature for a Networking it (probably) should
be targeted at net-next - as opposed to net, which is for bug fixes.
The target tree should be included in the subject.

  Subject: [PATCH net-next] ...

...

> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> index a0c2ef8bb0ac..24918d95f612 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
> @@ -127,6 +127,39 @@ static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
>  	writel(value, ioaddr + reg);
>  }
>  
> +static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,
> +				      u8 packet, u32 queue)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 value;
> +
> +	static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {
> +		{ XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },
> +		{ XGMAC_PTPQ, XGMAC_PTPQ_SHIFT },
> +		{ XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT },
> +		{ XGMAC_UPQ, XGMAC_UPQ_SHIFT },
> +		{ XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT },
> +	};
> +
> +	value = readl(ioaddr + XGMAC_RXQ_CTRL1);
> +
> +	/* routing configuration */
> +	value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
> +	value |= (queue << dwxgmac2_route_possibilities[packet-1].reg_shift) &
> +		dwxgmac2_route_possibilities[packet - 1].reg_mask;
> +
> +	/* some packets require extra ops */
> +	if (packet == PACKET_AVCPQ) {
> +		value &= ~XGMAC_TACPQE;
> +		value |= 0x1 << XGMAC_TACPQE_SHIFT;

FIELD_PREP seems appropriate here.

> +	} else if (packet == PACKET_MCBCQ) {
> +		value &= ~XGMAC_MCBCQEN;
> +		value |= 0x1 << XGMAC_MCBCQEN_SHIFT;

And here.

> +	}
> +
> +	writel(value, ioaddr + XGMAC_RXQ_CTRL1);
> +}
> +
>  static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
>  					    u32 rx_alg)
>  {

...