From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD4DEEE49AB for ; Fri, 25 Aug 2023 10:21:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244343AbjHYKUh (ORCPT ); Fri, 25 Aug 2023 06:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244454AbjHYKUQ (ORCPT ); Fri, 25 Aug 2023 06:20:16 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0ABC9E; Fri, 25 Aug 2023 03:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692958814; x=1724494814; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=lQJ7DKzc2oXt4rUd3d6tJI49oHr2VicpFOk6XH2iFSs=; b=PGOPyNvXX3PKk1ywgg/RNVC3wUMrMLd89fR8PT59BcvpU3X+XVnwgrux XTxZb1qX+9M+S/kTsu1EGMIwJ5VAOGzNdmkvRezR8NUs0mGFLP9gZaKe5 jgHhNvWvazj0enFbbAtji+3mMvE9FdqCxY8RJWDk1cdsuqz+nwHOcIsib MlBqRlQq/mPdn6lt7jnAc8+qesxASNyqUoOGjRXLneoOiZeoSNPL1NlRx lhlo74wpmZmk+wxx8ET5FK44wclLWlu9sr6ehf9M9/aeYiVidc5QiQc4A fvPFff7Ocfxw/MqAgXB2fiF+MxQ9a5m4Qxugaqb4WMv21epA5cwQbrsX1 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="378466533" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="378466533" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2023 03:19:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="984065698" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="984065698" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga006.fm.intel.com with ESMTP; 25 Aug 2023 03:19:40 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1qZTuk-00CiqI-2Y; Fri, 25 Aug 2023 13:19:38 +0300 Date: Fri, 25 Aug 2023 13:19:38 +0300 From: Andy Shevchenko To: Linhua Xu Cc: Linus Walleij , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, lh xu , Xiongpeng Wu Subject: Re: [PATCH 5/6] pinctrl: sprd: Increase the range of register values Message-ID: References: <20230825031826.31599-1-Linhua.xu@unisoc.com> <20230825031826.31599-6-Linhua.xu@unisoc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230825031826.31599-6-Linhua.xu@unisoc.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 25, 2023 at 11:18:25AM +0800, Linhua Xu wrote: > From: Linhua Xu > > As the UNISOC pin controller version iterates, more registers are required > to meet new functional requirements. Thus modify them. ... + bits.h and... > +#define NUM_OFFSET (22) > +#define TYPE_OFFSET (18) > +#define BIT_OFFSET (10) > +#define WIDTH_OFFSET (6) Why do you need parentheses? Also what do these represent (since they are decimal numbers)? ... > #define SPRD_PIN_INFO(num, type, offset, width, reg) \ > (((num) & 0xFFF) << NUM_OFFSET | \ > ((type) & 0xF) << TYPE_OFFSET | \ > ((offset) & 0xFF) << BIT_OFFSET | \ > ((width) & 0xF) << WIDTH_OFFSET | \ > - ((reg) & 0xF)) > + ((reg) & 0x1F)) ...use GENMASK() everywhere above. ... > .type = (((a) >> TYPE_OFFSET) & 0xf), \ > .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \ > .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \ > - .reg = ((a) & 0xf) \ > + .reg = ((a) & 0x1f) \ Ditto. -- With Best Regards, Andy Shevchenko