From: Robert Richter <rrichter@amd.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v12 01/20] cxl/port: Fix release of RCD endpoints
Date: Sun, 29 Oct 2023 17:17:38 +0100 [thread overview]
Message-ID: <ZT6Fov84g5FxrBEj@rric.localdomain> (raw)
In-Reply-To: <653c66507bf8d_244c8f294ea@dwillia2-xfh.jf.intel.com.notmuch>
On 27.10.23 18:39:28, Dan Williams wrote:
> Dan Williams wrote:
> > Robert Richter wrote:
> > > Dan,
> > [..]
> > >
> > > delete_endpoint() is called here, but the uport etc. is not unbound.
> > > Which means this is not true:
> > >
> > > if (parent->driver && !endpoint->dead) {
> > > ...
> > >
> > > I don't remember this with my patch. The parent is there different, so
> > > that could be the reason.
> > >
> > > I could not yet look into more detail but wanted to let you know. Will
> > > continue.
> >
> > Apologies, I didn't have that regression going, I think I see the issue.
> > Thanks for the heads up.
>
> Here is the incremental fix on top of the lifetime fix:
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 6230ddfc0be8..0fe915ec2cc2 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1217,30 +1217,39 @@ static struct device *grandparent(struct device *dev)
> return NULL;
> }
>
> +static struct device *endpoint_host(struct cxl_port *endpoint)
> +{
> + struct cxl_port *port = to_cxl_port(endpoint->dev.parent);
> +
> + if (is_cxl_root(port))
> + return port->uport_dev;
> + return &port->dev;
> +}
Yes, that works.
Reviewed-by: Robert Richter <rrichter@amd.com>
Tested-by: Robert Richter <rrichter@amd.com>
Thanks,
-Robert
next prev parent reply other threads:[~2023-10-29 16:17 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-18 17:16 [PATCH v12 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-10-18 17:16 ` [PATCH v12 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-27 3:46 ` Dan Williams
2023-10-27 22:55 ` Robert Richter
2023-10-28 0:32 ` Dan Williams
2023-10-28 1:39 ` Dan Williams
2023-10-29 16:17 ` Robert Richter [this message]
2023-10-18 17:16 ` [PATCH v12 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-27 20:04 ` Dan Williams
2023-10-18 17:16 ` [PATCH v12 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-18 17:16 ` [PATCH v12 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-18 17:16 ` [PATCH v12 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-10-18 17:16 ` [PATCH v12 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-10-18 17:17 ` [PATCH v12 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-27 21:51 ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-10-27 21:54 ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-10-18 17:17 ` [PATCH v12 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-19 14:30 ` Jonathan Cameron
2023-10-20 22:36 ` Robert Richter
2023-10-27 22:02 ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-27 22:12 ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-10-18 17:17 ` [PATCH v12 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-10-18 17:17 ` [PATCH v12 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-27 22:16 ` Dan Williams
2023-10-28 3:23 ` Dan Williams
2023-10-18 17:17 ` [PATCH v12 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-10-18 17:17 ` [PATCH v12 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-10-18 17:17 ` [PATCH v12 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-10-18 17:17 ` [PATCH v12 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-10-18 17:17 ` [PATCH v12 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-10-18 17:17 ` [PATCH v12 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
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