From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3900C61D85 for ; Thu, 23 Nov 2023 09:00:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231316AbjKWJAE (ORCPT ); Thu, 23 Nov 2023 04:00:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbjKWJAC (ORCPT ); Thu, 23 Nov 2023 04:00:02 -0500 Received: from mail11.truemail.it (mail11.truemail.it [IPv6:2001:4b7e:0:8::81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F1A3D49; Thu, 23 Nov 2023 01:00:09 -0800 (PST) Received: from francesco-nb.int.toradex.com (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 1476E206FC; Thu, 23 Nov 2023 10:00:06 +0100 (CET) Date: Thu, 23 Nov 2023 10:00:04 +0100 From: Francesco Dolcini To: Parth Pancholi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Francesco Dolcini , Marcel Ziswiler , Parth Pancholi , Conor Dooley , Krzysztof Kozlowski , Nishanth Menon , Rob Herring , Tero Kristo , Vignesh Raghavendra Subject: Re: [PATCH v1] arm64: dts: k3-am625-verdin: enable Verdin UART2 Message-ID: References: <20231121160436.1032364-1-parth105105@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231121160436.1032364-1-parth105105@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 21, 2023 at 05:04:36PM +0100, Parth Pancholi wrote: > From: Parth Pancholi > > Enable UART2 for AM62 based SOM's Verdin carrier boards Dahlia, > Development and Yavia. > Earlier Verdin UART2 was reserved by R5 DM firmware which can be now > configured using boardcfg during U-boot compilation in the latest TI > SDKs. In a default config, no one writes to this UART. > > Signed-off-by: Parth Pancholi Reviewed-by: Francesco Dolcini Francesco