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Wed, 03 Jan 2024 19:56:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEvUY09MTn5GToRw03eTFd2Z42WB1/U704H6N/ybGn6z8OeOBAp6ZdewL30cqW+xtKO4DZEgw== X-Received: by 2002:a05:6358:e497:b0:175:524e:440d with SMTP id by23-20020a056358e49700b00175524e440dmr2948348rwb.57.1704340613566; Wed, 03 Jan 2024 19:56:53 -0800 (PST) Received: from localhost.localdomain ([2804:431:c7ec:911:6911:ca60:846:eb46]) by smtp.gmail.com with ESMTPSA id nb5-20020a17090b35c500b0028bbf4c0264sm2558789pjb.10.2024.01.03.19.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 19:56:53 -0800 (PST) From: Leonardo Bras To: Guo Ren Cc: Leonardo Bras , Andrew Jones , paul.walmsley@sifive.com, palmer@dabbelt.com, panqinglin2020@iscas.ac.cn, bjorn@rivosinc.com, conor.dooley@microchip.com, peterz@infradead.org, keescook@chromium.org, wuwei2016@iscas.ac.cn, xiaoguang.xing@sophgo.com, chao.wei@sophgo.com, unicorn_wang@outlook.com, uwu@icenowy.me, jszhang@kernel.org, wefu@redhat.com, atishp@atishpatra.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Guo Ren Subject: Re: [PATCH V2 3/3] riscv: xchg: Prefetch the destination word for sc.w Date: Thu, 4 Jan 2024 00:56:39 -0300 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: <20231231082955.16516-1-guoren@kernel.org> <20231231082955.16516-4-guoren@kernel.org> <20240102-81391283df04c430d76c0eb0@orel> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Thu, Jan 04, 2024 at 09:24:40AM +0800, Guo Ren wrote: > On Thu, Jan 4, 2024 at 3:45 AM Leonardo Bras wrote: > > > > On Wed, Jan 03, 2024 at 02:15:45PM +0800, Guo Ren wrote: > > > On Tue, Jan 2, 2024 at 7:19 PM Andrew Jones wrote: > > > > > > > > On Sun, Dec 31, 2023 at 03:29:53AM -0500, guoren@kernel.org wrote: > > > > > From: Guo Ren > > > > > > > > > > The cost of changing a cacheline from shared to exclusive state can be > > > > > significant, especially when this is triggered by an exclusive store, > > > > > since it may result in having to retry the transaction. > > > > > > > > > > This patch makes use of prefetch.w to prefetch cachelines for write > > > > > prior to lr/sc loops when using the xchg_small atomic routine. > > > > > > > > > > This patch is inspired by commit: 0ea366f5e1b6 ("arm64: atomics: > > > > > prefetch the destination word for write prior to stxr"). > > > > > > > > > > Signed-off-by: Guo Ren > > > > > Signed-off-by: Guo Ren > > > > > --- > > > > > arch/riscv/include/asm/cmpxchg.h | 4 +++- > > > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > > > > index 26cea2395aae..d7b9d7951f08 100644 > > > > > --- a/arch/riscv/include/asm/cmpxchg.h > > > > > +++ b/arch/riscv/include/asm/cmpxchg.h > > > > > @@ -10,6 +10,7 @@ > > > > > > > > > > #include > > > > > #include > > > > > +#include > > > > > > > > > > #define __arch_xchg_masked(prepend, append, r, p, n) \ > > > > > > > > Are you sure this is based on v6.7-rc7? Because I don't see this macro. > > > Oh, it is based on Leobras' patches. I would remove it in the next of version. > > > > I would say this next :) > Thx for the grammar correction. Oh, I was not intending to correct grammar. I just meant the next thing I would mention is that it was based on top of my patchset instead of v6.7-rc7: > > > > > > > > > > > > > > > ({ \ > > > > > @@ -23,6 +24,7 @@ > > > > > \ > > > > > __asm__ __volatile__ ( \ > > > > > prepend \ > > > > > + PREFETCHW_ASM(%5) \ > > > > > "0: lr.w %0, %2\n" \ > > > > > " and %1, %0, %z4\n" \ > > > > > " or %1, %1, %z3\n" \ > > > > > @@ -30,7 +32,7 @@ > > > > > " bnez %1, 0b\n" \ > > > > > append \ > > > > > : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \ > > > > > - : "rJ" (__newx), "rJ" (~__mask) \ > > > > > + : "rJ" (__newx), "rJ" (~__mask), "rJ" (__ptr32b) \ > > > > > > > > I'm pretty sure we don't want to allow the J constraint for __ptr32b. > > > > > > > > > : "memory"); \ > > > > > \ > > > > > r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ > > > > > -- > > > > > 2.40.1 > > > > > > > > > > > > > Thanks, > > > > drew > > > > > > > > > > > > -- > > > Best Regards > > > Guo Ren > > > > > > > Nice patch :) > > Any reason it's not needed in __arch_cmpxchg_masked(), and __arch_cmpxchg() ? > CAS is a conditional AMO, unlike xchg (Stand AMO). Arm64 is wrong, or > they have a problem with the hardware. Sorry, I was unable to fully understand the reason here. You suggest that the PREFETCH.W was inserted on xchg_masked because it will always switch the variable (no compare, blind CAS), but not on cmpxchg. Is this because cmpxchg will depend on a compare, and thus it does not garantee a write? so it would be unwise to always prefetch cacheline exclusiveness for this cpu, where shared state would be enough. Is that correct? Thanks! Leo > > > > > Thanks! > > Leo > > > > > -- > Best Regards > Guo Ren >