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Fri, 11 Apr 2025 10:18:16 +0000 Date: Fri, 11 Apr 2025 12:18:03 +0200 From: Larysa Zaremba To: Raju Rangoju CC: , , , , , , , Subject: Re: [PATCH net-next 3/5] amd-xgbe: add support for new XPCS routines Message-ID: References: <20250408182001.4072954-1-Raju.Rangoju@amd.com> <20250408182001.4072954-4-Raju.Rangoju@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250408182001.4072954-4-Raju.Rangoju@amd.com> X-ClientProxiedBy: VI1P194CA0049.EURP194.PROD.OUTLOOK.COM (2603:10a6:803:3c::38) To SN7PR11MB7540.namprd11.prod.outlook.com (2603:10b6:806:340::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN7PR11MB7540:EE_|DM6PR11MB4724:EE_ X-MS-Office365-Filtering-Correlation-Id: d48b0860-71fa-4a73-f0ca-08dd78e22cc8 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|10070799003|7053199007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Rx0u3sehQR9/G8OLvnOBrmNKmw2pUR4g/B+ZT8jRLhm/ickXdGRpuH7P9GU9?= =?us-ascii?Q?d1LX6oR4PL/ZXCN4Db4AeAPsqC2taqedDLxqVbCo9QS2nzRtJTDGVLypn/J/?= =?us-ascii?Q?e8lU9BfdWZR26brIEyztOadJG3oDd/xVPpKnnNorr2tnZN5QBWfrESWV7hwN?= =?us-ascii?Q?R/E4jK9eCt+2pfhCcEdgaetabEsy4K9LuqQ31UtTym+P7iXDVy4GTlY4LE37?= =?us-ascii?Q?evpqyweIC0SCfXtxlh5aAh4bMrAOr0IkLoqTSosjzNHUVcrdzwwkuW4GwZ9p?= =?us-ascii?Q?+xzCzm6MXuntfC8lZbRieyJmsCh2GByKZox6UTbBWq24qbcYoz8pwV745G0E?= =?us-ascii?Q?4wTNXIydcZks3JX2urOULGthOTqoxvD1OVK3UaviGmb1TrpANypfRe7teo4q?= =?us-ascii?Q?CiENAkZcRxNPQd53wA5BqGi1zYTsCElpPPe7r10Nb/VSwKMCMbvuyE5HyHVK?= =?us-ascii?Q?PnMh4MiQFl4AwwAzil8gLN91SA2gYV/Qumn0E7eZZKBk9lV+OnmVsnrMCPjv?= =?us-ascii?Q?tvaYHMbWmV2H8n2nlkbK6YW+jP+ffo6M2puabOUeZPTdmm0I/dCTDYEP0jAw?= =?us-ascii?Q?QnmayIaZJjEO+wTK1WAJBFFuiHI3zAVgc3z6X6rBT7OYan+9/AO3FQOF1Ebb?= =?us-ascii?Q?qwU7Sp+pbT7Or+7c8daoUQ7YWX4hVVNK5BERa3e5M+qYjK6rd4OH5PMBLlDF?= =?us-ascii?Q?5Hgmk3NFGuRm8MHYyis2pbzv8VinXrUE1PrwILey7cgq8yjvS35yxjrS0GLB?= =?us-ascii?Q?7pTyieO6tcQ1qEfLk6Uq+ayAf4lhw9zsmqlJ6Oxix+4nZP9C3Ny7EAa8+lN7?= =?us-ascii?Q?3+88QwXEDtVoMlnjC1VL+OXRXv28zeke7WUBswGRi8/0/VC62IOq/7zDs8Fp?= =?us-ascii?Q?/ofTptCHy+CVIeCNLb0jLGMguvbj+QKJ5SZC1MxvD8OJFwIp/ehCjhCRuN3V?= =?us-ascii?Q?m5o2f8wBGgqBegGrHJCYLq1byW/B38fHoqcJa77m8dCtIctYcETweZ+w0Au1?= =?us-ascii?Q?zR544rMQhjxmpuVUQWD2Nm7HiqkTmeFOpV4FTvKwGY0GyZUqmdYaEb3uzwWd?= =?us-ascii?Q?i4nm+hFhJGN64rYdTAHngKpp6H9uicAMruY4U5nyIiJcp1+viMlNXp5WiCFr?= =?us-ascii?Q?9qKdTH7xIzElH0QAp30HPhaRt3v5qOfkn3aZnVjvbiwoOcN9OYoL7ysU5zOY?= =?us-ascii?Q?nUVRNf4VTZAySQ35wiRMs2+heMupjWmeMRpAxMpho8DIIeolE7oSJZvb0dN4?= =?us-ascii?Q?CTweoCa5AbUxbbgKgaLIc9AZKP8056OFHWvhCGpumEsdnCF3EGr47lY1JNBa?= =?us-ascii?Q?zxE3wR1CAQr9Fq3Q8cfbF4mgNHjUGv6lGfMGTkzYZJ5DSm5/pcbGW0T7mdKJ?= =?us-ascii?Q?njOpAL+NRgeXmp5V2HRwV0XxL2QLP5VxCc0gKwbJ5VftRWukd42NBAQRS7d5?= =?us-ascii?Q?ctkhfuI3nhbOjs8oAwrPwp2vFFDvM7H5Sv8RU2z9101PgNFN1tkZDLQZnzyW?= =?us-ascii?Q?fAbr6wDj6puhcY1pL4wRFaamkKZactskKnjdBKmMSyUolobTMHqAfhbFOlmz?= =?us-ascii?Q?7vzYStuEeEckqIJ271BTxiWKS9xymfN2Sh1btWQNKQvNHQ2hj/SDTjE0+DOa?= =?us-ascii?Q?0GyrC8QYQQCfz536n6pX3LaPsTxfUOYQIa4SIqe3z7ou8XOjajCNf029NnE8?= =?us-ascii?Q?Lu75gA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: d48b0860-71fa-4a73-f0ca-08dd78e22cc8 X-MS-Exchange-CrossTenant-AuthSource: SN7PR11MB7540.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 10:18:16.8313 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1XeNbh4OygVObxJi8xVGzgnewi7/w4vkct7dUtyTPIskQTOY5JEzCuxfusrWDVwrrXKpqbKXy+0Gw7qxMToQc5/q2AqsGlMvIBEsZv2IgVw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4724 X-OriginatorOrg: intel.com On Tue, Apr 08, 2025 at 11:49:59PM +0530, Raju Rangoju wrote: > Add the necessary support to enable Crater ethernet device. Since the > BAR1 address cannot be used to access the XPCS registers on Crater, use > the smn functions. > > Signed-off-by: Raju Rangoju > --- > drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 79 ++++++++++++++++++++++++ > drivers/net/ethernet/amd/xgbe/xgbe.h | 6 ++ > 2 files changed, 85 insertions(+) > > diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > index ae82dc3ac460..d75cf8df272f 100644 > --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > > #include "xgbe.h" > #include "xgbe-common.h" > @@ -1066,6 +1067,78 @@ static void get_pcs_index_and_offset(struct xgbe_prv_data *pdata, > *offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); > } > > +static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, > + int mmd_reg) > +{ > + unsigned int mmd_address, index, offset; > + struct pci_dev *rdev; > + unsigned long flags; > + int mmd_data; > + > + rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); > + if (!rdev) > + return 0; Why do you operate on the root device's config space? Is this SoC-specific, like in ixgbe_x550em_a_has_mii()? If so, would be nice to have a comment or at least something in the commit message. > + > + mmd_address = get_mmd_address(pdata, mmd_reg); > + > + get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); > + > + spin_lock_irqsave(&pdata->xpcs_lock, flags); > + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg)); > + pci_write_config_dword(rdev, 0x64, index); > + pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset); > + pci_read_config_dword(rdev, 0x64, &mmd_data); > + mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) : > + FIELD_GET(XGBE_GEN_LO_MASK, mmd_data); > + > + pci_dev_put(rdev); > + spin_unlock_irqrestore(&pdata->xpcs_lock, flags); > + > + return mmd_data; > +} > + > +static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, > + int mmd_reg, int mmd_data) > +{ > + unsigned int pci_mmd_data, hi_mask, lo_mask; > + unsigned int mmd_address, index, offset; > + struct pci_dev *rdev; > + unsigned long flags; > + > + rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); > + if (!rdev) > + return; > + > + mmd_address = get_mmd_address(pdata, mmd_reg); > + > + get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); > + > + spin_lock_irqsave(&pdata->xpcs_lock, flags); > + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg)); > + pci_write_config_dword(rdev, 0x64, index); > + pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset); > + pci_read_config_dword(rdev, 0x64, &pci_mmd_data); > + > + if (offset % 4) { > + hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data); > + lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, pci_mmd_data); > + } else { > + hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK, > + FIELD_GET(XGBE_GEN_HI_MASK, pci_mmd_data)); > + lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, mmd_data); > + } > + > + pci_mmd_data = hi_mask | lo_mask; > + > + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window_sel_reg)); > + pci_write_config_dword(rdev, 0x64, index); > + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset)); > + pci_write_config_dword(rdev, 0x64, pci_mmd_data); > + pci_dev_put(rdev); > + > + spin_unlock_irqrestore(&pdata->xpcs_lock, flags); > +} > + > static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, > int mmd_reg) > { > @@ -1160,6 +1233,9 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, > case XGBE_XPCS_ACCESS_V2: > default: > return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); > + > + case XGBE_XPCS_ACCESS_V3: > + return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg); > } > } > > @@ -1173,6 +1249,9 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, > case XGBE_XPCS_ACCESS_V2: > default: > return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); > + > + case XGBE_XPCS_ACCESS_V3: > + return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data); > } > } > > diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h > index 2e9b3be44ff8..6c49bf19e537 100644 > --- a/drivers/net/ethernet/amd/xgbe/xgbe.h > +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h > @@ -242,6 +242,10 @@ > #define XGBE_RV_PCI_DEVICE_ID 0x15d0 > #define XGBE_YC_PCI_DEVICE_ID 0x14b5 > > + /* Generic low and high masks */ > +#define XGBE_GEN_HI_MASK GENMASK(31, 16) > +#define XGBE_GEN_LO_MASK GENMASK(15, 0) > + > struct xgbe_prv_data; > > struct xgbe_packet_data { > @@ -460,6 +464,7 @@ enum xgbe_speed { > enum xgbe_xpcs_access { > XGBE_XPCS_ACCESS_V1 = 0, > XGBE_XPCS_ACCESS_V2, > + XGBE_XPCS_ACCESS_V3, > }; > > enum xgbe_an_mode { > @@ -951,6 +956,7 @@ struct xgbe_prv_data { > struct device *dev; > struct platform_device *phy_platdev; > struct device *phy_dev; > + unsigned int xphy_base; > > /* Version related data */ > struct xgbe_version_data *vdata; > -- > 2.34.1 > >