From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from elvis.franken.de (elvis.franken.de [193.175.24.41]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2736F763E4; Thu, 8 Feb 2024 12:49:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.175.24.41 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707396596; cv=none; b=d0Nr/f+7ma081radKxGGQCHdVceTUse6PkxPQQhCU0n5BCdms3KnbBZCv6l4k2tzwLdw40tseht9PoccG3//b2j9KYE3DaY/boWrus0U2EwrS9bxYxfItbc/fxtXbnvfjcIwH1+FGpQdyZQT3pcpiQ4yQ/C3hmLvhDC0ZAtOPIQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707396596; c=relaxed/simple; bh=/raue+ELhkH2hPh2pJ5EPvccB2rMfZ0AyREnP0RN1h4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=PuBEsCiJOflRC6iThJPN6gDHJcbZCEyOvBc54MZc0KVzffFSlGX/EGyEUX91lN6FP1X3B1XsLXsS1hYei0sS8oEiXAFk9XlYfKNy1AL4EtmZKEPlxIMAq5rrTYFl7JTAQBgl8+AnillPd+GTvP+eu3Sbjhp22GDbMueGchjlEK0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=alpha.franken.de; spf=pass smtp.mailfrom=alpha.franken.de; arc=none smtp.client-ip=193.175.24.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=alpha.franken.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alpha.franken.de Received: from uucp by elvis.franken.de with local-rmail (Exim 3.36 #1) id 1rY3Mr-000327-00; Thu, 08 Feb 2024 13:19:01 +0100 Received: by alpha.franken.de (Postfix, from userid 1000) id 71A38C0267; Thu, 8 Feb 2024 13:11:30 +0100 (CET) Date: Thu, 8 Feb 2024 13:11:30 +0100 From: Thomas Bogendoerfer To: Gregory CLEMENT Cc: Paul Burton , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?iso-8859-1?Q?Th=E9o?= Lebrun , Thomas Petazzoni Subject: Re: [PATCH v7 03/14] MIPS: Allows relocation exception vectors everywhere Message-ID: References: <20240205153503.574468-1-gregory.clement@bootlin.com> <20240205153503.574468-4-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240205153503.574468-4-gregory.clement@bootlin.com> On Mon, Feb 05, 2024 at 04:34:49PM +0100, Gregory CLEMENT wrote: > From: Jiaxun Yang > > Now the exception vector for CPS systems are allocated on-fly > with memblock as well. > > It will try to allocate from KSEG1 first, and then try to allocate > in low 4G if possible. > > The main reset vector is now generated by uasm, to avoid tons > of patches to the code. Other vectors are copied to the location > later. > > gc: use the new macro CKSEG[0A1]DDR_OR_64BIT() > move 64bits fix in an other patch > fix cache issue with mips_cps_core_entry > rewrite the patch to reduce the diff stat > Signed-off-by: Jiaxun Yang > Signed-off-by: Gregory CLEMENT > --- > arch/mips/include/asm/mips-cm.h | 1 + > arch/mips/include/asm/smp-cps.h | 4 +- > arch/mips/kernel/cps-vec.S | 48 ++------- > arch/mips/kernel/smp-cps.c | 171 +++++++++++++++++++++++++++----- > 4 files changed, 157 insertions(+), 67 deletions(-) > [..] > diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c > index dd55d59b88db3..f4cdd50177e0b 100644 > --- a/arch/mips/kernel/smp-cps.c > +++ b/arch/mips/kernel/smp-cps.c > @@ -7,6 +7,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -25,7 +26,34 @@ > #include > #include > > +#define BEV_VEC_SIZE 0x500 > +#define BEV_VEC_ALIGN 0x1000 > + > +#define A0 4 > +#define A1 5 > +#define T9 25 > +#define K0 26 > +#define K1 27 > + > +#define C0_STATUS 12, 0 > +#define C0_CAUSE 13, 0 > + > +#define ST0_NMI_BIT 19 > +#ifdef CONFIG_64BIT > +#define ST0_KX_IF_64 ST0_KX > +#else > +#define ST0_KX_IF_64 0 > +#endif please move this together with the other defines in arch/mips/kvm/entry.c to a header file (arch/mips/include/asm/uasm.h sounds like a good fit). > +static void __init setup_cps_vecs(void) > +{ > + extern void excep_tlbfill(void); > + extern void excep_xtlbfill(void); > + extern void excep_cache(void); > + extern void excep_genex(void); > + extern void excep_intex(void); > + extern void excep_ejtag(void); I know this used a lot in arch/mips, but don't add another one and put this to a header file. IMHO checkpatch should have warned you about that. > + /* We want to ensure cache is clean before writing uncached mem */ > + blast_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); > + bc_wback_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); > + __sync(); how about doint the generation with cached memory and flush caches after that ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]