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Fri, 21 Jun 2024 11:20:16 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45LBKFpL027039 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jun 2024 11:20:15 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 21 Jun 2024 04:20:09 -0700 Date: Fri, 21 Jun 2024 16:50:05 +0530 From: Varadarajan Narayanan To: Dmitry Baryshkov CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v1 5/7] clk: qcom: gcc-ipq9574: Add CPR clock definition Message-ID: References: <20240620081427.2860066-1-quic_varada@quicinc.com> <20240620081427.2860066-6-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PtMB4z0B8foTTy1Ntbh4XdDN-9b72SOY X-Proofpoint-GUID: PtMB4z0B8foTTy1Ntbh4XdDN-9b72SOY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-21_04,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406210083 On Thu, Jun 20, 2024 at 06:11:32PM +0300, Dmitry Baryshkov wrote: > On Thu, Jun 20, 2024 at 01:44:25PM GMT, Varadarajan Narayanan wrote: > > Add the CPR clock definition needed for enabling access to > > CPR register space. > > > > Signed-off-by: Varadarajan Narayanan > > --- > > drivers/clk/qcom/gcc-ipq9574.c | 38 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > > index e1dc74d04ed1..7c8eb94f654b 100644 > > --- a/drivers/clk/qcom/gcc-ipq9574.c > > +++ b/drivers/clk/qcom/gcc-ipq9574.c > > @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { > > }, > > }; > > > > +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { > > + F(24000000, P_XO, 1, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 rbcpr_clk_src = { > > + .cmd_rcgr = 0x48044, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gcc_xo_map, > > + .freq_tbl = ftbl_gp1_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "rbcpr_clk_src", > > + .parent_data = gcc_xo_gpll0_gpll4, > > + .num_parents = ARRAY_SIZE(gcc_xo_map), > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_branch gcc_rbcpr_clk = { > > + .halt_reg = 0x48008, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x48008, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gcc_rbcpr_clk", > > + .parent_hws = (const struct clk_hw *[]) { > > + &rbcpr_clk_src.clkr.hw, > > Where is the &rbcpr_clk_src registered? Oops. Missed it. Will post a corrected patch. Thanks Varada > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > static struct clk_hw *gcc_ipq9574_hws[] = { > > &gpll0_out_main_div2.hw, > > &gcc_xo_div4_clk_src.hw, > > @@ -4219,6 +4256,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { > > [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, > > [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, > > [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, > > + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, > > }; > > > > static const struct qcom_reset_map gcc_ipq9574_resets[] = { > > -- > > 2.34.1