Subject: [PATCH] mtd: spi-nor: add support for MRAM Everspin EM008LXB

[<claus.fabig@emerson.com>]

From: Claus Fabig <claus.fabig@emerson.com>
Date: Thu, 18 Jul 2024 09:53:36 +0200
Subject: [PATCH] mtd: spi-nor: add support for MRAM Everspin EM008LXB

The Everspin EM008LXB MRAM has 8Mb and is populated on a custom board
using Microchip's PCI12000 spi host controller running on low 30MHz clock.
According to Everspin Read Fast (0xb) command below 60MHz is neither
specified and nor tested. Test shows that using Read Fast (0xb) will
result in reading inconsistent data in this setup but writing is fine, so
only supporting Read (0x3) command should be acceptable for the moment.
The device is JEDEC compatible (JESD251 and JESD251-1) but not able to
provide SFDP information.

For spec v3.2 refer to www.everspin.com/file/158315/download.

Successfully tested according to
www.kernel.org/doc/html/latest/driver-api/mtd/spi-nor.html:

cat /sys/bus/spi/devices/spi-EMR5555\:00/spi-nor/partname
em008lxb

cat /sys/bus/spi/devices/spi-EMR5555\:00/spi-nor/manufacturer
everspin

cat /sys/kernel/debug/spi-nor/spi-EMR5555\:00/capabilities
Supported read modes by the flash
 1S-1S-1S
  opcode        0x03
  mode cycles   0
  dummy cycles  0

Supported page program modes by the flash
 1S-1S-1S
  opcode        0x02

cat /sys/kernel/debug/spi-nor/spi-EMR5555\:00/params
name            em008lxb
id              (null)
size            1.00 MiB
write size      1
page size       256
address nbytes  3
flags           HAS_SR_TB | HAS_16BIT_SR | HAS_4BIT_BP | HAS_SR_BP3_BIT6

opcodes
 read           0x03
  dummy cycles  0
 erase          0xd8
 program        0x02
 8D extension   none

protocols
 read           1S-1S-1S
 write          1S-1S-1S
 register       1S-1S-1S

erase commands
 d8 (1.00 MiB) [0]
 c7 (1.00 MiB)

sector map
 region (in hex)   | erase mask | overlaid
 ------------------+------------+----------
 00000000-000fffff |     [0   ] | no

cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00020000 00020000 "spi-EMR1010:00"
mtd1: 00100000 00100000 "spi-EMR5555:00"

mtd_debug info /dev/mtd1
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 1048576 (1M)
mtd.erasesize = 1048576 (1M)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0

dd if=/dev/urandom of=spi_test bs=1M count=1
mtd_debug erase /dev/mtd1 0 1048576
mtd_debug read /dev/mtd1 0 1048576 spi_read
Copied 1048576 bytes from address 0x00000000 in flash to spi_read
hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0100000
sha256sum spi_read
f5fb04aa5b882706b9309e885f19477261336ef76a150c3b4d3489dfac3953ec  spi_read
mtd_debug write /dev/mtd1 0 1048576 spi_test
Copied 1048576 bytes from spi_test to address 0x00000000 in flash
mtd_debug read /dev/mtd1 0 1048576 spi_read
Copied 1048576 bytes from address 0x00000000 in flash to spi_read
sha256sum spi*
cf9a1f3f4089602d194d67d1a918a574a5ca1d9aa71d391a661818c1f0ee1aab  spi_read
cf9a1f3f4089602d194d67d1a918a574a5ca1d9aa71d391a661818c1f0ee1aab  spi_test

Signed-off-by: claus.fabig@emerson.com
---
 drivers/mtd/spi-nor/core.c     | 2 +-
 drivers/mtd/spi-nor/everspin.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index e0c4efc424f4..95267d9e8b65 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3713,7 +3713,7 @@ static const struct spi_device_id spi_nor_dev_ids[] = {
 	{ "mr25h256" }, /* 256 Kib, 40 MHz */
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
-
+	{ "em008lxb" }, /*   8 Mib, 133 MHz */
 	{ },
 };
 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index add37104d673..c1f004c39c1c 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -31,6 +31,11 @@ static const struct flash_info everspin_nor_parts[] = {
 		.size = SZ_512K,
 		.sector_size = SZ_512K,
 		.flags = SPI_NOR_NO_ERASE,
+	}, {
+		.name = "em008lxb",
+		.size = SZ_1M,
+		.sector_size = SZ_1M,
+		.flags = SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6,
 	}
 };
 
-- 
2.45.2